GB2041703A - Coding, decoding, digital data - Google Patents

Abstract

In a technique for the transmission or for the non-saturating recording and replaying of serial digital data, the data is converted into a coded signal in which each digit is represented by a respective pulse code having a positive value and a negative value, the time integral of each pulse code being equal to zero as shown in Figure 1. In order to decode this signal, it is applied to a threshold device for sensing when it passes upper and lower thresholds and for producing an output signal having upper and lower levels in response thereto (Figure 3b). This output signal is applied to an integrator which generates a triangular signal having rising ramps corresponding to one of the levels of the output signal and falling ramps corresponding to the other level. A threshold detector receives the triangular signal and generates therefrom a decoded signal and a clock signal. <IMAGE>

Description

SPECIFICATION Coding apparatus This invention relates to a coding apparatus for use in information storage or transmission, and a decoding apparatus for subsequently recovering that information. One particular application of the invention is in relation to recording on a magnetic medium such as a magnetic tape, and this application is described in detail below. However, it should be appreciated that the invention is also applicable to other fields, for example the transmission of information by radio techniques or along a line, for example a telephone line.

According to the invention there is provided an apparatus for converting serial digital information into a coded signal for storage or transmission, comprising an input for receiving serial digital information, and means for generating from each digit a respective pulse code having a positive value and a negative value, the time integral of each pulse code being equal to zero.

In the accompanying drawings: Figure 1 shows a waveform as produced by the coding apparatus of the present invention; Figure 2 shows an embodiment of the coding apparatus of the present invention in relation to magnetic tape recording; Figures 3a to 3e show successive stages in the decoding of a recorded waveform; and Figure 4 shows a circuit for carrying out the stages of Figures 3a to 3e.

The modulated waveform used in the present invention has three possible levels, namely zero, negative or positive. It can remain at zero indefinitely (e.g. for an inter-block gap) but can only remain positive or negative for defined equal intervals or a multiple thereof. Figure 1 shows a representative waveform with arbitrarily ascribed digital significances, whereby the waveform represents 1101. The direction of the first excursion is always the same; this is significant for playback, as is shown later. It can be seen that each bit starts and ends at zero and has a zero nett voltage time product. This means that, providing no saturation occurs, a recording will produce no nett residual flux in the recording head (this of course refers to the application of the invention to magnetic recording).

The waveform is recorded using current feed to the head and pre-emphasis as is normal audio practice. The level is high but not saturating. A suitable recording circuit is shown in Figure 2 and its action described later.

During replay the recorded information is first amplified and compensated in the normal way, resulting in a waveform which is the same as the recorded waveform within the frequency and amplitude response limitations of the medium (see Figure 3a). A more exact reconstruction is then achieved by feeding the amplified signal into a bipolar threshold switch, the upper and lower switch thresholds being shown in Figure 3a. The switch remains at zero unless the input exceeds a certain threshold, in which case the output switches to a defined positive or negative voltage, as appropriate (see Figure 3b).

The regenerated waveform is decoded by feeding it into a clamped and biassed integrator acting as a time-to-voltage converter. The output of the integrator is a substantially triangular signal which has positive ramps when the input signal is at its defined negative voltage, negative ramps when the input signal is at its defined positive voltage, and is substantially constant during the brief transitions between the said positive and negative values. The logic "O"s, being twice as long as the logic "1"s, will produce twice the output voltage from the integrator. Two comparators sense the integrator output, one being below the logic "1" level, the other below the logic "0" level. The former (see Figure 3d) will always be tripped, thereby re-forming the clock, whereas the latter will only trip for a logic "0" (see Figure 3e), and represents the decoded output.

The noise immunity is provided a) by the threshold switch, which will not switch on noise and remains at its full output unless the input waveform recrosses the threshold (the threshold may alse be made larger before tripping than after by the application of hysteresis), and b) by the integrator, which will cause misreading only if the voltage time product from the threshold switch is grossly in error (due to large missing or wrong polarity sections caused by excessive noise).

Speed errors will similarly only cause reading errors if they are so large as to cause the integrator output to cross the higher threshold erroneously, or fail to cross the lower threshold.

Figure 2 shows an embodiment of recording circuit realized in CMOS and based on a 3.2768 MHz clock using a 1600 Hz cycle as a "1" and an 800 Hz cycle as a "0". (3.2768 MHz is a common digital clock crystal frequency). Note that the fre#quency ratio is arbitary; 2:1 provides a reasonable compromise between the need for an adequate degree of differentiation between "O"s and "1"s and the need not to use an excessive bandwidth.

Assume the initial quiescent state: "Run Tape" is low and therefore "Tape not ready" which is fed to one input of an OR gate 5, is high (this is arranged to go low when recording if the tape is present and has reached the correct recording speed). This results in bi-stable 3 being reset, Q high. Divider 1 is therefore held reset via AND gate 4. Interconnected inputs of OR gate 10 and of EXOR gate 11 are held high resulting in point A being high and point B low.

Since resistors 12 and 13 are of equal value, point C, which is connected to the mutual connection of resistors 12 and 13, will sit at the half rail point.

Capacitor 16 will be charged to this voltage via resistor 23.

Diodes 17 and 18 allow a replay amplifier (see Figure 4) to be permanently connected to the record replay head by isolating the recording circuit noise voltage. However they produce negligible attenuation of the actual recording signal when in the record mode. Capacitors 14 and 15 are respectively connected in parallel to the resistors 12 and 13 to provide the necessary recording pre-emphasis.

To commence recording, "Run Tape" is commanded, enabling AND gate 2. Presently, when the tape reaches the correct speed, "Tape not ready" will go low removing the reset from bi-stable 3 and divider 1. Two clock edges later bi-stable 3 is cleared as the "1" on D is clocked through. Q goes low and the "send data bit" line, which is connected thereto by an inverter gate 54, goes high, requesting data from the data source and causing points A and B to go low. The first part of the recording waveform of Figure 1 has now been produced.

The serial data source, which provides serial binary data in conventional form, has approximately half of a 1600 Hz period, i.e. approximately 300 us in which to respond with a "1" or "O" as appropriate, so that the inputs to AND gates 6,7 and inverter gate 8 can select the correct transition from the divider outputs. If a "1" is required then the 1600 Hz output is selected by AND gate 7 and causes point "A" to go high, and hence point "B", during the second half of the 1600 Hz cycle. At the end of the 1600 Hz cycle the 800 Hz output goes high and causes bi-stable 3 to be reset via gates 6 and 5, thus causing divider 1 to be reset and starting the cycle of events again.

If the "data in" line remains at a zero after 300 us from the start of a cycle then the polarity changeover at gates 10 and 11 does not occur until half way through the 800 Hz cycle, as selected by gate 9. The end of the cycle is signalled by the 400 Hz output going high, re-setting the system via gate 5.

At the end of a group of data, "Run Tape" is set low, thereby not clearing the reset of bistable 3 produced at the end of a cycle. The circuit of Figure 2 thus generates a waveform of the type shown in Figure 1 from a conventional binary data signal. This signal is provided to the record/replay head 19 for recording on a magnetic medium such as a magnetic tape.

Figure 4 shows an embodiment of playback circuit which also incorporates an automatic demagnetizing facility.

High gain amplifier 25, along with resistors 20,22 and 23 and capacitors 21 and 24 forms a feedback amplifier with frequency shaping to provide the necessary replay characterstic, as in normal audio practice.

The amplified compensated signal as in Figure 3a, is fed via a resistor 26 into a threshold switch. In Figure 4, the section above the OV line is the positive threshold switch, and the section below the line is the negative threshold switch. Thus, the positive threshold switch comprises transistors 27 and 32, and resistors 28, 29, 30 and 43, and the negative threshold switch comprises transistors 33 and 34, and resistors 37, 36,35 and 38. The resistors 29 and 36 provide hysteresis for the positive and negative switches respectively.

In the quiescent state the transistors 32 and 34 are turned on, producing near zero voltages at points A and B. Input resistors 39 and 40 of an integrating amplifier 50 having a capacitor 45 connected across it are equal and hence diodes 41 and 42 ensure a net current into the integrator virtual earth, thereby holding the output against a clamp diode 44.

The first signal excursion at the threshold switch is negative and causes the output point B to switch negative, causing the integrator output to ramp positive. The following positive signal excursion causes point B to return to near zero and point A to go positive, causing the integrator output to return to the clamp level. The resistor 43 is smaller in value than resistor 38 to ensure the return of the integrator output to the clamp level.

The effect of voltage changes at points A and B are summed by the integrator to give the effect of the single input shown in Figure 3b.

Comparators 46 and 47, which are connected to the output of the integrator, have inputs V1 and V2 arranged so that they switch for the "1" and "0" levels respectively (see Figure 3c) so that their outputs are as shown in Figures 3d and 3e. The output of a bi-stable 48 to which the comparator outputs are connected is sampled on the negative edge of the "clock out" line, a high representing a "1" and a low representing a "O".

Attention is also drawn to resistors 31 and 53 and capacitor 51,which form a signal averager. Any difference in the voltage-time product of negative and positive switch excursions will cause a net voltage to be developed across the capacitor 51.

Such a difference would be caused if the tape head 19 were magnetized resulting in saturation during one polarity of the recording signal. Any voltage across the capacitor 51 causes a current to flow through the head 19 via a resistor 52. This is in such a direction as to cause a magnetic flux counteracting the original magnetization.

The invention and embodiments thereof allow the use of standard audio recording heads and tape for medium speed recording of serial data and ensures that the head cannot become permanently magnetized. There is good noise immunity with high packing density and a self clocking effect. The noise immunity is not derived from the use of phaselocked loops, as is usually the case, but is the result of using a biassed integrator. This has the advantage of not requiring a phase-locked loop settling time at the beginning of a data block. The self clocking nature means that large speed variations (+ 20%) have no effect, and no separate clock track is needed on the tape. The recording waveform can be obtained direct from standard logic integrated circuits.

Claims (13)

1. An apparatus for converting serial digital information into a coded signal for storage or transmission, comprising an input for receiving serial digital information, and means for generating from each digit a respective pulse code having a positive value and a negative value, the time integral of each pulse code being equal to zero.

2. An apparatus according to claim 1, wherein each pulse code has the same shape, the different pulse codes being distinguished from one another by their duration.

3. An apparatus according to claim 2, wherein the duration of the pulse codes are each equal to the multiple of a respective integer and a basic predetermined duration.

4. An apparatus according to any preceding claim, wherein each pulse code consists of one negative pulse and one positive pulse.

5. An apparatus according to any preceding claim, wherein the serial digital information is binary information.

6. An apparatus for converting serial digital information into coded form, substantially as herein described with reference to Figures 1 and 2 of the accompanying drawings.

7. A recording device employing a magnetic recording medium and comprising an apparatus according to any preceding claim.

8. A device according to claim 7, wherein the said magnetic medium is a magnetic tape.

9. An apparatus for decoding a signal stored or transmitted by means of apparatus according to any one of claims 1 to 6, comprising an input for receiving the said information, a threshold device for sensing when the signal passes upper and lower thresholds and producing an output signal having upper and lower signal levels in response thereto, an integrator arranged to receive the said output signal and generate therefrom a triangular signal which has rising ramps corresponding to the portions of the said output signal which are at one of the said levels and falling ramps corresponding to the portions of the said output signal which are at the other of the said levels, and a threshold detector arranged to receive the said triangular signal and generate therefrom a decoded signal constituting the original serial digital information.

10. An apparatus according to claim 9, wherein the threshold detector is arranged also to generate from the said triangular signal a clock signal.

11. An apparatus according to claim 9 or 10, comprising means for detecting any difference between the time integrals of the said positive and negative values and generating a difference signal in response thereto.

12. An apparatus according to claim 11, which is in the form of a replay apparatus for replaying information stored in magnetic form using a magnetic head, and wherein the said difference signal is arranged to be fed back to the said head to compensate for magnetization of the head.

13. An apparatus for decoding a signal stored or transmitted by means of an apparatus according to any one of claims 1 to 6, substantially as herein described with reference to Figures 3 and 4 of the accompanying drawings.