JPS5797170A - Control system - Google Patents
Control systemInfo
- Publication number
- JPS5797170A JPS5797170A JP17358880A JP17358880A JPS5797170A JP S5797170 A JPS5797170 A JP S5797170A JP 17358880 A JP17358880 A JP 17358880A JP 17358880 A JP17358880 A JP 17358880A JP S5797170 A JPS5797170 A JP S5797170A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- timing
- circuit
- idle
- inputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
Abstract
PURPOSE:To raise the processing efficiency, by detecting a working state of prescribed timing, and idle timing, and starting the next access from the idle timing. CONSTITUTION:A processing instruction is inputted to a decoder 20, and the instruction converted to a code is inputted to an insturction start controlling circuit 21. The instruction start controlling circuit 21 detects an idle timing by an idle detecting circuit 22 of a bank timing in accordance with the inputted instruction, and also detects a working state of the first ooerand by a detecting circuit 23. Moreover, the instruction is inputted to a multiplying instruction and adding instruction processing and controlling circuit 24 and 27, respectively, the timing of the banks which said circuits are using is controlled by controlling circuits 25, 28, the residual cycle number of said mutiplication and addition is controlled by controlling circuits 26, 29, and it is informed to the instruction start controlling circuit 21 that said residual cycle number is <=10. The instruction start controlling circuit 21 gives a command to start the instruction, to a vector register, by the idle detecting signal of the bank timing in its own circuit, and a signal informing that the residual cycle number is <=10.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17358880A JPS5797170A (en) | 1980-12-09 | 1980-12-09 | Control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17358880A JPS5797170A (en) | 1980-12-09 | 1980-12-09 | Control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5797170A true JPS5797170A (en) | 1982-06-16 |
Family
ID=15963358
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17358880A Pending JPS5797170A (en) | 1980-12-09 | 1980-12-09 | Control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5797170A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61202281A (en) * | 1985-03-05 | 1986-09-08 | Fujitsu Ltd | Pipeline control system |
JPS61269774A (en) * | 1985-05-24 | 1986-11-29 | Fujitsu Ltd | Vector instruction executing and controlling system |
-
1980
- 1980-12-09 JP JP17358880A patent/JPS5797170A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61202281A (en) * | 1985-03-05 | 1986-09-08 | Fujitsu Ltd | Pipeline control system |
JPH0479027B2 (en) * | 1985-03-05 | 1992-12-14 | Fujitsu Ltd | |
JPS61269774A (en) * | 1985-05-24 | 1986-11-29 | Fujitsu Ltd | Vector instruction executing and controlling system |
JPH0477945B2 (en) * | 1985-05-24 | 1992-12-09 | Fujitsu Ltd |
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