JPS5795627A - Method for arranging mark in electron beam exposure - Google Patents

Method for arranging mark in electron beam exposure

Info

Publication number
JPS5795627A
JPS5795627A JP17088580A JP17088580A JPS5795627A JP S5795627 A JPS5795627 A JP S5795627A JP 17088580 A JP17088580 A JP 17088580A JP 17088580 A JP17088580 A JP 17088580A JP S5795627 A JPS5795627 A JP S5795627A
Authority
JP
Japan
Prior art keywords
marks
mark
wafer
positions
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17088580A
Other languages
Japanese (ja)
Inventor
Korehito Matsuda
Kiichi Takamoto
Tsuneo Okubo
Norio Saito
Hisatake Yokouchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP17088580A priority Critical patent/JPS5795627A/en
Publication of JPS5795627A publication Critical patent/JPS5795627A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/304—Controlling tubes by information coming from the objects or from the beam, e.g. correction signals
    • H01J37/3045—Object or beam position registration

Abstract

PURPOSE:To improve a yield rate by arranging aligning marks and spare marks with a specified interval being provided on a plurality of positions on scribing lines, saving mark occupying areas on chips, and making it possible to compensate displacement when the marks are damaged. CONSTITUTION:A plurality of chips 4 on a wafer 1 is grouped in one block. The aligning marks 2 are arranged at e.g. four positions in each block. The shift of the position of the pattern due to the distortion of the wafer 1 is checked and compensated, and the scribing is performed. In the vicinity of each mark 2, the spare mark 3 is arranged with a specified interval being provided. The positions of the marks 2 and 3 are located in the region of the scribe lines provided for dividing the chip into four areas. In this method, the mark occupying area can be saved, several marks 2 and 3 can be provided for every location. Even though the mark 2 is damaged during the treating process of the wafer 1, the distortion compensation can be accurately performed and the yield rate of the chip 4 can be improved.
JP17088580A 1980-12-05 1980-12-05 Method for arranging mark in electron beam exposure Pending JPS5795627A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17088580A JPS5795627A (en) 1980-12-05 1980-12-05 Method for arranging mark in electron beam exposure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17088580A JPS5795627A (en) 1980-12-05 1980-12-05 Method for arranging mark in electron beam exposure

Publications (1)

Publication Number Publication Date
JPS5795627A true JPS5795627A (en) 1982-06-14

Family

ID=15913113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17088580A Pending JPS5795627A (en) 1980-12-05 1980-12-05 Method for arranging mark in electron beam exposure

Country Status (1)

Country Link
JP (1) JPS5795627A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074519A (en) * 1983-09-30 1985-04-26 Fujitsu Ltd Specimen aligning process in electron beam exposure
US4564764A (en) * 1982-09-30 1986-01-14 Fujitsu Limited Wafer having chips for determining the position of the wafer by means of electron beams
JPH10312067A (en) * 1997-05-09 1998-11-24 Canon Inc Exposure method and aligner
CN106206224A (en) * 2015-05-31 2016-12-07 Fei 公司 The dynamic creation of standby benchmark

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108287A (en) * 1977-03-03 1978-09-20 Fujitsu Ltd Manufacture of semiconductor device
JPS53135578A (en) * 1977-04-30 1978-11-27 Fujitsu Ltd Mark protection method
JPS5498268A (en) * 1978-01-16 1979-08-03 Ibm Method of inspecting position

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108287A (en) * 1977-03-03 1978-09-20 Fujitsu Ltd Manufacture of semiconductor device
JPS53135578A (en) * 1977-04-30 1978-11-27 Fujitsu Ltd Mark protection method
JPS5498268A (en) * 1978-01-16 1979-08-03 Ibm Method of inspecting position

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4564764A (en) * 1982-09-30 1986-01-14 Fujitsu Limited Wafer having chips for determining the position of the wafer by means of electron beams
JPS6074519A (en) * 1983-09-30 1985-04-26 Fujitsu Ltd Specimen aligning process in electron beam exposure
JPH10312067A (en) * 1997-05-09 1998-11-24 Canon Inc Exposure method and aligner
CN106206224A (en) * 2015-05-31 2016-12-07 Fei 公司 The dynamic creation of standby benchmark
EP3101679A1 (en) * 2015-05-31 2016-12-07 FEI Company Dynamic creation of backup fiducials
US9619728B2 (en) 2015-05-31 2017-04-11 Fei Company Dynamic creation of backup fiducials

Similar Documents

Publication Publication Date Title
FR2388371A1 (en) ALIGNMENT PROCEDURE, IN A PHOTOREPEATER, OF A SEMICONDUCTOR PLATE AND THE PATTERNS TO BE PROJECTED AND PHOTOREPEATER USING SUCH A PROCESS
JPS57112021A (en) Manufacture of semiconductor device
JPS6442128A (en) Semiconductor substrate with alignment mark formed thereon
DE3580192D1 (en) METHOD FOR PRODUCING A CONTACT FOR A SEMICONDUCTOR ARRANGEMENT.
JPS5795627A (en) Method for arranging mark in electron beam exposure
JPS57204127A (en) Drawing method for pattern of electron-ray drawing device
FR2571545B1 (en) METHOD FOR MANUFACTURING A SUBSTRATE OF HYBRID CIRCUIT OF NON-PLANAR SHAPE, AND HYBRID NON-PLANAR CIRCUIT OBTAINED BY THIS PROCESS
JPS55162219A (en) Semiconductor wafer
JPS6459231A (en) Mask layout method for semiconductor integrated circuit
KR950013722A (en) Manufacturing method of thermal printhead
JPS5745236A (en) Manufacture of semiconductor device
JPS5534430A (en) Positioning method in electron beam exposure
JPS5735333A (en) Inspection equipment of semiconductor wafer
JPS57166034A (en) Positioning method
JPS5721826A (en) Manufacture of semiconductor single crystal wafer
JPS57109335A (en) Positional matching method between mask substrate and wafer
JPS6425412A (en) Method of controlling chip position
JPH0226636Y2 (en)
KR960014964B1 (en) Manufacturing method of semiconductor device
KR950027942A (en) Photomask Alignment in Wafer
DE3576056D1 (en) METHOD FOR PRODUCING AN INTEGRATED SEMICONDUCTOR CIRCUIT USING AN ORGANIC FILM.
JPS5359370A (en) Positioning method
JPS6457635A (en) Semiconductor device
JPS6184649A (en) Photomask
KR100256267B1 (en) Photomask having laser mark