JPS5794858A - Address tracing system - Google Patents

Address tracing system

Info

Publication number
JPS5794858A
JPS5794858A JP55169587A JP16958780A JPS5794858A JP S5794858 A JPS5794858 A JP S5794858A JP 55169587 A JP55169587 A JP 55169587A JP 16958780 A JP16958780 A JP 16958780A JP S5794858 A JPS5794858 A JP S5794858A
Authority
JP
Japan
Prior art keywords
address
register
memory
traced
tracing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55169587A
Other languages
Japanese (ja)
Inventor
Yoshito Hagiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55169587A priority Critical patent/JPS5794858A/en
Publication of JPS5794858A publication Critical patent/JPS5794858A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To reduce the interruption of a program and to obtain a desired result of tracing, by previously setting plural addresses to be traced to a memory, etc. CONSTITUTION:The addresses to be traced are written into a memory 1 in the desired order of tracing. An address including the head address of the trace address is set to a reading register 4, and the address read out of the memory 1 is set to the register 4. A comparator 6 compares the contents between the register 4 and a program counter 5. When a coincidence is obtained, the contents of a reading address register 3 is replaced. Then a stored address is set to the register 4 from the memory 1. The above-mentioned actions are repeated.
JP55169587A 1980-12-03 1980-12-03 Address tracing system Pending JPS5794858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55169587A JPS5794858A (en) 1980-12-03 1980-12-03 Address tracing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55169587A JPS5794858A (en) 1980-12-03 1980-12-03 Address tracing system

Publications (1)

Publication Number Publication Date
JPS5794858A true JPS5794858A (en) 1982-06-12

Family

ID=15889241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55169587A Pending JPS5794858A (en) 1980-12-03 1980-12-03 Address tracing system

Country Status (1)

Country Link
JP (1) JPS5794858A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5981740A (en) * 1982-10-30 1984-05-11 Nec Corp Information processor
JPS6292033A (en) * 1985-10-17 1987-04-27 Omron Tateisi Electronics Co Program debugging device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5981740A (en) * 1982-10-30 1984-05-11 Nec Corp Information processor
JPS6292033A (en) * 1985-10-17 1987-04-27 Omron Tateisi Electronics Co Program debugging device

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