JPS5783921A - Frequency multiplying circuit - Google Patents

Frequency multiplying circuit

Info

Publication number
JPS5783921A
JPS5783921A JP15972380A JP15972380A JPS5783921A JP S5783921 A JPS5783921 A JP S5783921A JP 15972380 A JP15972380 A JP 15972380A JP 15972380 A JP15972380 A JP 15972380A JP S5783921 A JPS5783921 A JP S5783921A
Authority
JP
Japan
Prior art keywords
turns
resistance
input signal
terminal
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15972380A
Other languages
Japanese (ja)
Inventor
Masaaki Kanda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15972380A priority Critical patent/JPS5783921A/en
Publication of JPS5783921A publication Critical patent/JPS5783921A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To realize small-sized constitution by connecting a series circuit of complementary transistors (TR), whose gates are connected in common, and a resistance in series between a power source and an earth, and by leading an output from both terminals of the resistance. CONSTITUTION:When an input signal applied to an input terminal rises from a low to a high level, an N channel TR8 turns on and a current flows through a P channel TR turning on continuously, developing a voltage across a resistance 10. Therefore, an N channel TR9 turns on and a terminal has a low level. When the input signal further rises, the TR turns off and the current flowing through the resistance 10 disappears; and the TR9 turns off, and the terminal 2 has a high level. When the input signal falls, the same operations are performed, thus obtaining an output at the terminal 2 when the input signal rises and falls.
JP15972380A 1980-11-13 1980-11-13 Frequency multiplying circuit Pending JPS5783921A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15972380A JPS5783921A (en) 1980-11-13 1980-11-13 Frequency multiplying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15972380A JPS5783921A (en) 1980-11-13 1980-11-13 Frequency multiplying circuit

Publications (1)

Publication Number Publication Date
JPS5783921A true JPS5783921A (en) 1982-05-26

Family

ID=15699865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15972380A Pending JPS5783921A (en) 1980-11-13 1980-11-13 Frequency multiplying circuit

Country Status (1)

Country Link
JP (1) JPS5783921A (en)

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