JPS5779653A - Lead frame for resin-sealed semiconductor device - Google Patents
Lead frame for resin-sealed semiconductor deviceInfo
- Publication number
- JPS5779653A JPS5779653A JP15635480A JP15635480A JPS5779653A JP S5779653 A JPS5779653 A JP S5779653A JP 15635480 A JP15635480 A JP 15635480A JP 15635480 A JP15635480 A JP 15635480A JP S5779653 A JPS5779653 A JP S5779653A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- lead
- lead frame
- tin
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000007747 plating Methods 0.000 abstract 3
- 239000000615 nonconductor Substances 0.000 abstract 2
- 239000011347 resin Substances 0.000 abstract 2
- 229920005989 resin Polymers 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000000465 moulding Methods 0.000 abstract 1
- 238000007789 sealing Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15635480A JPS5779653A (en) | 1980-11-06 | 1980-11-06 | Lead frame for resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15635480A JPS5779653A (en) | 1980-11-06 | 1980-11-06 | Lead frame for resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5779653A true JPS5779653A (en) | 1982-05-18 |
| JPS6130749B2 JPS6130749B2 (enrdf_load_stackoverflow) | 1986-07-15 |
Family
ID=15625916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15635480A Granted JPS5779653A (en) | 1980-11-06 | 1980-11-06 | Lead frame for resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5779653A (enrdf_load_stackoverflow) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4876587A (en) * | 1987-05-05 | 1989-10-24 | National Semiconductor Corporation | One-piece interconnection package and process |
| US4942455A (en) * | 1986-10-13 | 1990-07-17 | Mitsubishi Denki Kabushiki Kaisha | Lead frame for a semiconductor device and a method for manufacturing a semiconductor device using the lead frame |
| US4985749A (en) * | 1988-03-22 | 1991-01-15 | Bull S.A. | Substrate for very large scale integrated circuit and apparatus for selective tinning of the substrate leads |
-
1980
- 1980-11-06 JP JP15635480A patent/JPS5779653A/ja active Granted
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4942455A (en) * | 1986-10-13 | 1990-07-17 | Mitsubishi Denki Kabushiki Kaisha | Lead frame for a semiconductor device and a method for manufacturing a semiconductor device using the lead frame |
| US5026669A (en) * | 1986-10-13 | 1991-06-25 | Mitsubishi Denki Kabushiki Kaisha | Method of eliminating burrs on a lead frame with a thin metal coating |
| US4876587A (en) * | 1987-05-05 | 1989-10-24 | National Semiconductor Corporation | One-piece interconnection package and process |
| US4985749A (en) * | 1988-03-22 | 1991-01-15 | Bull S.A. | Substrate for very large scale integrated circuit and apparatus for selective tinning of the substrate leads |
| US5081949A (en) * | 1988-03-22 | 1992-01-21 | Bull S.A. | Apparatus for selective tinning of substrate leads |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6130749B2 (enrdf_load_stackoverflow) | 1986-07-15 |
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