JPS5779556A - Microprogram control system - Google Patents

Microprogram control system

Info

Publication number
JPS5779556A
JPS5779556A JP15353680A JP15353680A JPS5779556A JP S5779556 A JPS5779556 A JP S5779556A JP 15353680 A JP15353680 A JP 15353680A JP 15353680 A JP15353680 A JP 15353680A JP S5779556 A JPS5779556 A JP S5779556A
Authority
JP
Japan
Prior art keywords
microinstruction
branch
register
address
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15353680A
Other languages
Japanese (ja)
Inventor
Toshio Nakamura
Shuichi Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP15353680A priority Critical patent/JPS5779556A/en
Publication of JPS5779556A publication Critical patent/JPS5779556A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection

Abstract

PURPOSE:To decrease the number of microinstruction by executing a following microinstruction according to whether the control is returned to a branch origin or not, by providing a state holding circuit which informs that a branch to a subroutine is done when a microinstruction for the branch is executed. CONSTITUTION:When a microinstruction in an address indicated by an address register 2 is read to a data register 3 to specify a microorder CALL, a decoder 4 decodes the contents into a return address from a subroutine to hold it in a return address register 5, and a following branch address is set from a control storage address field CMAF to the register 2; and further, a branch state holding circuit (flip-flop) 6 is set by the microinstruction order CALL to perform branching operation. Once a microinstruction order RTN is specified, a control circuit 7 discriminates the state of the circuit 6; when it is in an on-state, the return address is transferred to the register 2 for returning the control to the branch origin, and when in an off-state control over the execution of the following microinstruction is exercised.
JP15353680A 1980-10-31 1980-10-31 Microprogram control system Pending JPS5779556A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15353680A JPS5779556A (en) 1980-10-31 1980-10-31 Microprogram control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15353680A JPS5779556A (en) 1980-10-31 1980-10-31 Microprogram control system

Publications (1)

Publication Number Publication Date
JPS5779556A true JPS5779556A (en) 1982-05-18

Family

ID=15564655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15353680A Pending JPS5779556A (en) 1980-10-31 1980-10-31 Microprogram control system

Country Status (1)

Country Link
JP (1) JPS5779556A (en)

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