JPS577933A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS577933A
JPS577933A JP8320580A JP8320580A JPS577933A JP S577933 A JPS577933 A JP S577933A JP 8320580 A JP8320580 A JP 8320580A JP 8320580 A JP8320580 A JP 8320580A JP S577933 A JPS577933 A JP S577933A
Authority
JP
Japan
Prior art keywords
pattern
etching
etched
magnitude
intervals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8320580A
Other languages
Japanese (ja)
Inventor
Shuji Kanamori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8320580A priority Critical patent/JPS577933A/en
Publication of JPS577933A publication Critical patent/JPS577933A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To observe and judge the dimensions of the pattern to be etched based on the variation in the intervals between the slits, by etching the checking patterns which are so arranged that the intervals between a plurality of the slits have specified relationship with respect to the magnitude of the intervals, together with the pattern to be etched. CONSTITUTION:On the same substrate, are etched the pattern to be etched 1 having a designed central width W and maximum allowable deviation values l and u of the dimensions and the dimension checking patterns 2 at the same time. The checking patterns 2 are so arranged that the intervals between the pattern 2-1 and 2-6 having the designed central width W become gradually larger by DELTAW. That is W3=W and W5=W4+DELTAW. Suppose W=1mum, observe and compare the magnitude of the pattern to be etched after etching, and check the magnitude of the equivalent checking pattern 2-1 after etching. Then check that which interval width after etching correscponds to the magnitude of the checking pattern. Then the deviation of the etching is computed. In this method, the dimensions can be judged by observation without actual measurement of the pattern to be etched after etching.
JP8320580A 1980-06-19 1980-06-19 Manufacture of semiconductor device Pending JPS577933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8320580A JPS577933A (en) 1980-06-19 1980-06-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8320580A JPS577933A (en) 1980-06-19 1980-06-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS577933A true JPS577933A (en) 1982-01-16

Family

ID=13795818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8320580A Pending JPS577933A (en) 1980-06-19 1980-06-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS577933A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS609736U (en) * 1983-06-30 1985-01-23 栃木富士産業株式会社 hub clutch
US4650744A (en) * 1984-07-17 1987-03-17 Nec Corporation Method of manufacturing semiconductor device
JPS6366934A (en) * 1986-04-10 1988-03-25 Nec Corp Manufacture of semiconductor integrated circuit device using check pattern
JPH0265151A (en) * 1988-05-17 1990-03-05 British Telecommun Plc <Bt> Line width loss measuring method
CN105914160A (en) * 2016-04-07 2016-08-31 上海华力微电子有限公司 Method for improving bonding technology defect between ultrathin stack devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52103963A (en) * 1976-02-26 1977-08-31 Toshiba Corp Semiconductor device and its manufacturing method
JPS5427708A (en) * 1977-08-03 1979-03-02 Pioneer Electronic Corp Signal compander
JPS5453864A (en) * 1977-10-05 1979-04-27 Sanyo Electric Co Ltd Monitoring method of line widths

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52103963A (en) * 1976-02-26 1977-08-31 Toshiba Corp Semiconductor device and its manufacturing method
JPS5427708A (en) * 1977-08-03 1979-03-02 Pioneer Electronic Corp Signal compander
JPS5453864A (en) * 1977-10-05 1979-04-27 Sanyo Electric Co Ltd Monitoring method of line widths

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS609736U (en) * 1983-06-30 1985-01-23 栃木富士産業株式会社 hub clutch
JPS6345383Y2 (en) * 1983-06-30 1988-11-25
US4650744A (en) * 1984-07-17 1987-03-17 Nec Corporation Method of manufacturing semiconductor device
US5005071A (en) * 1984-07-17 1991-04-02 Nec Corporation Semiconductor device
JPS6366934A (en) * 1986-04-10 1988-03-25 Nec Corp Manufacture of semiconductor integrated circuit device using check pattern
JPH0265151A (en) * 1988-05-17 1990-03-05 British Telecommun Plc <Bt> Line width loss measuring method
CN105914160A (en) * 2016-04-07 2016-08-31 上海华力微电子有限公司 Method for improving bonding technology defect between ultrathin stack devices

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