JPS5776933A - Superheterodyne receiver - Google Patents
Superheterodyne receiverInfo
- Publication number
- JPS5776933A JPS5776933A JP55152721A JP15272180A JPS5776933A JP S5776933 A JPS5776933 A JP S5776933A JP 55152721 A JP55152721 A JP 55152721A JP 15272180 A JP15272180 A JP 15272180A JP S5776933 A JPS5776933 A JP S5776933A
- Authority
- JP
- Japan
- Prior art keywords
- power
- signal
- frequency
- oscillator
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
- H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
- H04W52/0274—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof
- H04W52/028—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof switching on or off only a part of the equipment circuit blocks
- H04W52/0283—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof switching on or off only a part of the equipment circuit blocks with sequential power up or power down of successive circuit blocks, e.g. switching on the local oscillator before RF or mixer stages
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
- H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
- H04W52/0287—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Superheterodyne Receivers (AREA)
- Circuits Of Receivers In General (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Transceivers (AREA)
Abstract
PURPOSE:To decrease the power consumption even with the use of a phase locked loop frequency synthesizer, by energizing the power for a short time at every pause time predetermined for a frequency divider which consumes a high power. CONSTITUTION:A signal from an antenna 1 is mixed with a local oscillation frequency signal from a line 4 at a mixture circuit 3 via a high-frequency amplifying circuit 2 and outputted from a speaker 8 via an IF amplifying circuit 5 and a demodulation circuit 6. On the line 4, a signal from a voltage-controlled oscillator 10 of a phase locked loop frequency synthesizer 9 is introduced, and the output of the oscillator 10 is inputted to a phase comparator 13 via a frequency divider 12 and it is compared with a signal from a reference frequency oscillator 14. Power is energized for a power energizing period for a short time with a switch 20 and the storage operation for a memory 18 is made during this period.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55152721A JPS5776933A (en) | 1980-10-29 | 1980-10-29 | Superheterodyne receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55152721A JPS5776933A (en) | 1980-10-29 | 1980-10-29 | Superheterodyne receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5776933A true JPS5776933A (en) | 1982-05-14 |
Family
ID=15546690
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55152721A Pending JPS5776933A (en) | 1980-10-29 | 1980-10-29 | Superheterodyne receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5776933A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6429026A (en) * | 1987-07-23 | 1989-01-31 | Nec Corp | Radio communication equipment |
-
1980
- 1980-10-29 JP JP55152721A patent/JPS5776933A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6429026A (en) * | 1987-07-23 | 1989-01-31 | Nec Corp | Radio communication equipment |
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