JPS56128013A - Synthesizer receiver - Google Patents
Synthesizer receiverInfo
- Publication number
- JPS56128013A JPS56128013A JP3102080A JP3102080A JPS56128013A JP S56128013 A JPS56128013 A JP S56128013A JP 3102080 A JP3102080 A JP 3102080A JP 3102080 A JP3102080 A JP 3102080A JP S56128013 A JPS56128013 A JP S56128013A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency
- voltage
- aft
- local
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
- H03J7/02—Automatic frequency control
- H03J7/04—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
- H03J7/06—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant using counters or frequency dividers
- H03J7/065—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant using counters or frequency dividers the counter or frequency divider being used in a phase locked loop
Abstract
PURPOSE:To prevent leading-in of an adjacent channel by operating a PLL circuit, when the local oscillating frequency has deviated over the allowable width in the course of holding a channel selection state by the AFT circuit. CONSTITUTION:A local oscillation signal of the tuner 1 is provided to the phase comparator circuit 13 through the frequency dividing circuit 12, and it is compared with the reference frequency fr of the oscillating circuit 14. This comparison output Ep is converted to the channel selection voltage Ei through the integrating circuit 16. On the other hand, a signal of the intermediate frequency amplifier 2 is converted to the AFT voltage Ea, and is made the voltage Ei through the integrating circuit 16. When the AFT voltage Ea is varied and has led in an adjacent channel, deviation of the local oscillator frequency becomes large. In this case, the comparator circuit 13 operates the PLL20 by its output, and sets the local oscillating frequency to a normal value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3102080A JPS56128013A (en) | 1980-03-12 | 1980-03-12 | Synthesizer receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3102080A JPS56128013A (en) | 1980-03-12 | 1980-03-12 | Synthesizer receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56128013A true JPS56128013A (en) | 1981-10-07 |
Family
ID=12319831
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3102080A Pending JPS56128013A (en) | 1980-03-12 | 1980-03-12 | Synthesizer receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56128013A (en) |
-
1980
- 1980-03-12 JP JP3102080A patent/JPS56128013A/en active Pending
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