JPS57750A - Decimal arithmetic system - Google Patents

Decimal arithmetic system

Info

Publication number
JPS57750A
JPS57750A JP7279280A JP7279280A JPS57750A JP S57750 A JPS57750 A JP S57750A JP 7279280 A JP7279280 A JP 7279280A JP 7279280 A JP7279280 A JP 7279280A JP S57750 A JPS57750 A JP S57750A
Authority
JP
Japan
Prior art keywords
arithmetic
decimal
microinstruction
specified
carries
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7279280A
Other languages
Japanese (ja)
Inventor
Nobuyuki Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7279280A priority Critical patent/JPS57750A/en
Publication of JPS57750A publication Critical patent/JPS57750A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To speed arithmetic by simplifying decimal addition by controlling input data in the next arithmetic cycle with stored carries by an arithmetic circuit which has no decimal arithmetic function.
CONSTITUTION: Every microinstruction is provided with a decimal arithmetic specifying part and decimal correcting FFs 9 and 10 operate only when decimal arithmetic is specified by the microinstruction; and carries of binary adders 1 and 2 when it is specified are stored to control outputs of registers 5 and 6 during arithmetic in the next cycle. When a carry is issued, its output is made zero and when not, an arithmetic result is outputted as it is. Therefore, a circuit wherein a decimal augend and a decimal addend each consisting of an optional number of digits are simplified adds respective digits in parallel at a relatively high speed.
COPYRIGHT: (C)1982,JPO&Japio
JP7279280A 1980-06-02 1980-06-02 Decimal arithmetic system Pending JPS57750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7279280A JPS57750A (en) 1980-06-02 1980-06-02 Decimal arithmetic system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7279280A JPS57750A (en) 1980-06-02 1980-06-02 Decimal arithmetic system

Publications (1)

Publication Number Publication Date
JPS57750A true JPS57750A (en) 1982-01-05

Family

ID=13499589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7279280A Pending JPS57750A (en) 1980-06-02 1980-06-02 Decimal arithmetic system

Country Status (1)

Country Link
JP (1) JPS57750A (en)

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