JPS5771582A - Operation system of semiconductor memory - Google Patents

Operation system of semiconductor memory

Info

Publication number
JPS5771582A
JPS5771582A JP55147904A JP14790480A JPS5771582A JP S5771582 A JPS5771582 A JP S5771582A JP 55147904 A JP55147904 A JP 55147904A JP 14790480 A JP14790480 A JP 14790480A JP S5771582 A JPS5771582 A JP S5771582A
Authority
JP
Japan
Prior art keywords
becomes
trs
information
pulse voltage
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55147904A
Other languages
Japanese (ja)
Inventor
Kaoru Tokushige
Masayoshi Nakane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55147904A priority Critical patent/JPS5771582A/en
Priority to US06/311,923 priority patent/US4403306A/en
Priority to DE3141555A priority patent/DE3141555C2/en
Publication of JPS5771582A publication Critical patent/JPS5771582A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To prevent volatilization of memory information, by constituting a memory so taht written information can be made nonvolatile, by 2 kinds of pulses which are inputted to the gate of an MNOS transistor. CONSTITUTION:Immediately after supply voltage Vcc has been turned on, when a negative pulse voltage is applied to both gates of N-MNOS transistors TR15, 16 from a pulse voltage signal line MG, by use of non-volatile information, the TRs 15, 16 become a depression type. As a result, the memory cell becomes a static RAM cnstituted of a general C-MOS. In this case, immediately before the supply Vcc becomes off, positive pulse voltage is applied to the TRs 15, 16 from the line MG. At this time, a difference arises in each voltage between the channel and the gate of the TRs 15, 16, and one of the TRs 15, 16 becomes a depression type and the other becomes an enhancement type. Accordingly, by this discrimination, the memory cell is capable of storing the information, and the written information becomes non-volatile.
JP55147904A 1980-10-22 1980-10-22 Operation system of semiconductor memory Pending JPS5771582A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP55147904A JPS5771582A (en) 1980-10-22 1980-10-22 Operation system of semiconductor memory
US06/311,923 US4403306A (en) 1980-10-22 1981-10-16 Semiconductor memory operable as static RAM or EAROM
DE3141555A DE3141555C2 (en) 1980-10-22 1981-10-20 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55147904A JPS5771582A (en) 1980-10-22 1980-10-22 Operation system of semiconductor memory

Publications (1)

Publication Number Publication Date
JPS5771582A true JPS5771582A (en) 1982-05-04

Family

ID=15440754

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55147904A Pending JPS5771582A (en) 1980-10-22 1980-10-22 Operation system of semiconductor memory

Country Status (1)

Country Link
JP (1) JPS5771582A (en)

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