JPS577143A - Substrate for carrying semiconductor - Google Patents

Substrate for carrying semiconductor

Info

Publication number
JPS577143A
JPS577143A JP8169580A JP8169580A JPS577143A JP S577143 A JPS577143 A JP S577143A JP 8169580 A JP8169580 A JP 8169580A JP 8169580 A JP8169580 A JP 8169580A JP S577143 A JPS577143 A JP S577143A
Authority
JP
Japan
Prior art keywords
bed
spot facing
elements
substrate
dumbbel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8169580A
Other languages
Japanese (ja)
Other versions
JPS6237887B2 (en
Inventor
Takeyumi Abe
Osamu Fujikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Toshiba Corp
Ibigawa Electric Industry Co Ltd
Original Assignee
Ibiden Co Ltd
Toshiba Corp
Ibigawa Electric Industry Co Ltd
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd, Toshiba Corp, Ibigawa Electric Industry Co Ltd, Tokyo Shibaura Electric Co Ltd filed Critical Ibiden Co Ltd
Priority to JP8169580A priority Critical patent/JPS577143A/en
Publication of JPS577143A publication Critical patent/JPS577143A/en
Publication of JPS6237887B2 publication Critical patent/JPS6237887B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To shorten the working time and lower the cost with a simplified process of working substrates by spot facing a bed for forming them to be loaded with chips in an oval or roughly in a dumbbel. CONSTITUTION:A substrate 10 undergoes a spot facing to form a bed 11 for elements 13 to be carried to ensure smaller size as a whole by making the elements almost equal in the height to the wiring pattern 12 to be provided on the surface thereof. The bed 11 is shaped in an oval or roughly in a dumbbel by means of a spot facing tool 11a with a circular tip. In the former case, the device 11a moves in one way while in the latter case, twice cutting is essential. The width W and the length L of the bed is set according to the shape of the elements 13. This simplifiers the spot facing thereby shortening the working time along with a lower cost.
JP8169580A 1980-06-17 1980-06-17 Substrate for carrying semiconductor Granted JPS577143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8169580A JPS577143A (en) 1980-06-17 1980-06-17 Substrate for carrying semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8169580A JPS577143A (en) 1980-06-17 1980-06-17 Substrate for carrying semiconductor

Publications (2)

Publication Number Publication Date
JPS577143A true JPS577143A (en) 1982-01-14
JPS6237887B2 JPS6237887B2 (en) 1987-08-14

Family

ID=13753499

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8169580A Granted JPS577143A (en) 1980-06-17 1980-06-17 Substrate for carrying semiconductor

Country Status (1)

Country Link
JP (1) JPS577143A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0353472A (en) * 1989-07-20 1991-03-07 Nobuyuki Odagiri Power plug with appliance name display in braille
JPH0353473A (en) * 1989-07-20 1991-03-07 Nobuyuki Odagiri Power plug with appliance name display

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5384681A (en) * 1976-12-29 1978-07-26 Mitsumi Electric Co Ltd Method of producing leadless package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5384681A (en) * 1976-12-29 1978-07-26 Mitsumi Electric Co Ltd Method of producing leadless package

Also Published As

Publication number Publication date
JPS6237887B2 (en) 1987-08-14

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