JPS576957A - File transfer system - Google Patents
File transfer systemInfo
- Publication number
- JPS576957A JPS576957A JP8117280A JP8117280A JPS576957A JP S576957 A JPS576957 A JP S576957A JP 8117280 A JP8117280 A JP 8117280A JP 8117280 A JP8117280 A JP 8117280A JP S576957 A JPS576957 A JP S576957A
- Authority
- JP
- Japan
- Prior art keywords
- transfer
- bus
- memory
- processor
- file
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
PURPOSE:To prevent the deterioration of processing capacity for a processor, by providing newly a transfer bus between a memory and a file and thus securing an independent transfer between an optional block of the memory and the file. CONSTITUTION:A transfer of data is carried out via a bus 22 between a memory 23 consisting of memory blocks 23a-23c and a processor 21. The transfer of data between the memory 23 and a file 26 is carried out independently from the transfer of data between the memory 23 and the processor 21 and between the block 23a and the file 26 after cutting off an optional block such as 23a from the bus 22 via a bus control circuit 24a and then connecting the cut-off block to a bus 27. When the processor 21 gives an access to the block 23a, an interruption signal is produced or the block 23a is connected to the bus 22 and then to the bus 27 again after an end of transfer of data to the processor 21. In such a way, a discontinuation is not required for the transfer of data between a processor and a memory during a transfer between a memory and a file. Accordingly the deterioration of processing capacity of a processor due to a bus holding can be prevented.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8117280A JPS576957A (en) | 1980-06-16 | 1980-06-16 | File transfer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8117280A JPS576957A (en) | 1980-06-16 | 1980-06-16 | File transfer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS576957A true JPS576957A (en) | 1982-01-13 |
Family
ID=13739035
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8117280A Pending JPS576957A (en) | 1980-06-16 | 1980-06-16 | File transfer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS576957A (en) |
-
1980
- 1980-06-16 JP JP8117280A patent/JPS576957A/en active Pending
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