JPS5763935A - Bootstrap circuit - Google Patents
Bootstrap circuitInfo
- Publication number
- JPS5763935A JPS5763935A JP55139471A JP13947180A JPS5763935A JP S5763935 A JPS5763935 A JP S5763935A JP 55139471 A JP55139471 A JP 55139471A JP 13947180 A JP13947180 A JP 13947180A JP S5763935 A JPS5763935 A JP S5763935A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- gate
- voltage
- output
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
- H03K19/01714—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To lessen the lowering of an output level by clamping the gate voltage of the 1st load transistor (TR) to a power voltage by the output of the 2nd boostihg circuit. CONSTITUTION:A level at a terminal 2 is determined by the ratio of the ON resistance of the 1st load TR3 which is connected to an output terminal 2 at the source, to a power source 29 at the drain and to the output point 11 of the 1st boosting circuit at the gate and that of the 1st driver TR4 which is connected to the terminal 2 at the drain, grounded at the source and to a control input terminal 1 at the gate. The TR33 is connected to the power source 29 at the drain, to the gate of the TR3 at the source, and to the output point 18 of the 2nd boosting circuit at the gate through a boosting capacitor (C) 34 to clamp a voltage at the output point 11 to a power voltage V. To the terminal 2, a boosting C27 whose one terminal is connected to the output point 26 of the 3rd boosting circuit is connected. When a level at the output point 18 rises, the gate voltage of the TR3 is clamped to the power voltage through the C34 and TR33, so the lowering of the voltage level at the terminal is reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55139471A JPS5763935A (en) | 1980-10-03 | 1980-10-03 | Bootstrap circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55139471A JPS5763935A (en) | 1980-10-03 | 1980-10-03 | Bootstrap circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5763935A true JPS5763935A (en) | 1982-04-17 |
Family
ID=15246007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55139471A Pending JPS5763935A (en) | 1980-10-03 | 1980-10-03 | Bootstrap circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5763935A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60254920A (en) * | 1984-05-31 | 1985-12-16 | Fujitsu Ltd | Mos buffer circuit |
| JPS6367814A (en) * | 1986-09-09 | 1988-03-26 | Nec Corp | Clock generator |
| US5369320A (en) * | 1992-07-22 | 1994-11-29 | Oki Electric Industry Co., Ltd. | Bootstrapped high-speed output buffer |
-
1980
- 1980-10-03 JP JP55139471A patent/JPS5763935A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60254920A (en) * | 1984-05-31 | 1985-12-16 | Fujitsu Ltd | Mos buffer circuit |
| JPS6367814A (en) * | 1986-09-09 | 1988-03-26 | Nec Corp | Clock generator |
| US5369320A (en) * | 1992-07-22 | 1994-11-29 | Oki Electric Industry Co., Ltd. | Bootstrapped high-speed output buffer |
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