JPS5752208A - Field effect transistor amplifying circuit - Google Patents

Field effect transistor amplifying circuit

Info

Publication number
JPS5752208A
JPS5752208A JP55126675A JP12667580A JPS5752208A JP S5752208 A JPS5752208 A JP S5752208A JP 55126675 A JP55126675 A JP 55126675A JP 12667580 A JP12667580 A JP 12667580A JP S5752208 A JPS5752208 A JP S5752208A
Authority
JP
Japan
Prior art keywords
current
fet8
fet6
source
same characteristics
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55126675A
Other languages
Japanese (ja)
Inventor
Yoshio Uchiumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55126675A priority Critical patent/JPS5752208A/en
Publication of JPS5752208A publication Critical patent/JPS5752208A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE: To obtain an output signal whose linearly is satisfactory, by constituting so that an input signal and a reverse signal are applied to two FETs having the same characteristics, respectively, and supplying a difference of each drain of each FET to a load.
CONSTITUTION: When an input signal Vi is supplied to an input terminal T1, a current i1 flows to the drain of an FET6. Since an FET3 and an FET4 have the same characteristics, a reverse signal of -Vi is generated between the source and the gate of the FET4, and is supplied to an FET8. Since the FET6 and the FET8 have the same characteristics, when a difference current between a current i2 flowing out from the source of the FET8, and the current i1 flowing to the FET6 is denoted as i3, a current flowing to a load 11 becomes a value which has subtracted the difference current i3 from a current I flowing out from a constant-current source 10. When voltage V0 across the load resistance 11 is outputted as an output signal, the output signal whose linearity is satisfactory to the input signal is obtained.
COPYRIGHT: (C)1982,JPO&Japio
JP55126675A 1980-09-12 1980-09-12 Field effect transistor amplifying circuit Pending JPS5752208A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55126675A JPS5752208A (en) 1980-09-12 1980-09-12 Field effect transistor amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55126675A JPS5752208A (en) 1980-09-12 1980-09-12 Field effect transistor amplifying circuit

Publications (1)

Publication Number Publication Date
JPS5752208A true JPS5752208A (en) 1982-03-27

Family

ID=14941070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55126675A Pending JPS5752208A (en) 1980-09-12 1980-09-12 Field effect transistor amplifying circuit

Country Status (1)

Country Link
JP (1) JPS5752208A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6360845A (en) * 1986-08-30 1988-03-16 Tadahiro Yuki Method for feeding out plurality of original film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6360845A (en) * 1986-08-30 1988-03-16 Tadahiro Yuki Method for feeding out plurality of original film

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