JPS5755436A - Test system for bus coupler - Google Patents

Test system for bus coupler

Info

Publication number
JPS5755436A
JPS5755436A JP55130441A JP13044180A JPS5755436A JP S5755436 A JPS5755436 A JP S5755436A JP 55130441 A JP55130441 A JP 55130441A JP 13044180 A JP13044180 A JP 13044180A JP S5755436 A JPS5755436 A JP S5755436A
Authority
JP
Japan
Prior art keywords
signal
memories
test mode
test
coupler
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55130441A
Other languages
Japanese (ja)
Inventor
Nobuteru Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55130441A priority Critical patent/JPS5755436A/en
Publication of JPS5755436A publication Critical patent/JPS5755436A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Abstract

PURPOSE:To make test for a coupler only with memories, by setting a device coupling common buses mutually to which various devices are connected in a test mode with commands of a central processing unit and fixing the output of memory reference lines. CONSTITUTION:Common buses 1-3 having central processing units (CPUs) 20, 21, IO control sections 10-32, and memories 40-42, are coupled with couplers 10 and 11 consisting of bus interfaces 50 and 52, transfer circuit 51 and control circuit 15. The control circuit 15 is provided with a signal conversion circuit consisting of a decoder 120, test mode storage 130 and OR gate 110. When the CPU gives a command of a test mode set, the decoder 120 is operated, a signal 121 turns on, the FF 130 is set, the output signal is transmitted to the OR gate 110, and signal line 101 is kept to 1 independently of the signal value on the signal line 100. Thus, all the addresses via a coupler are interpreted as memory addresses, and the test is executed only with memories without the IO control section.
JP55130441A 1980-09-19 1980-09-19 Test system for bus coupler Pending JPS5755436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55130441A JPS5755436A (en) 1980-09-19 1980-09-19 Test system for bus coupler

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55130441A JPS5755436A (en) 1980-09-19 1980-09-19 Test system for bus coupler

Publications (1)

Publication Number Publication Date
JPS5755436A true JPS5755436A (en) 1982-04-02

Family

ID=15034311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55130441A Pending JPS5755436A (en) 1980-09-19 1980-09-19 Test system for bus coupler

Country Status (1)

Country Link
JP (1) JPS5755436A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5161162A (en) * 1990-04-12 1992-11-03 Sun Microsystems, Inc. Method and apparatus for system bus testability through loopback

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5161162A (en) * 1990-04-12 1992-11-03 Sun Microsystems, Inc. Method and apparatus for system bus testability through loopback

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