JPS57100679A - Buffer memory device - Google Patents

Buffer memory device

Info

Publication number
JPS57100679A
JPS57100679A JP55175415A JP17541580A JPS57100679A JP S57100679 A JPS57100679 A JP S57100679A JP 55175415 A JP55175415 A JP 55175415A JP 17541580 A JP17541580 A JP 17541580A JP S57100679 A JPS57100679 A JP S57100679A
Authority
JP
Japan
Prior art keywords
cpu400
memory device
buffer memory
data
control part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55175415A
Other languages
Japanese (ja)
Inventor
Yasuyuki Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55175415A priority Critical patent/JPS57100679A/en
Publication of JPS57100679A publication Critical patent/JPS57100679A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To connect each device without unnecessary redundancy by perform- ing data transfer processing which corresponds to a specification signal from a CPU by connecting the CPU, a main memory device, and a data processing unit through a buffer memory device. CONSTITUTION:Accrding to two kinds of command signals from a CPU400, the 1st and 2nd control parts 120 and 130 are selected through the operation mode control part 140 of a buffer memory device (BM) 130. Then, data from a main storage device (MEM) 200 connecting with the CPU400 together with a data processing unit (DPU) 300 by a common bus 230 through the BM under the control of the control part 120 is written in the RAM100 of the BM110 and also transferred to the CPU400. When a control part 140 is selected, on the other hand, the data of the MEM200 is transferred to the CPU400 through the DPU 300. In this constitution, the BM100, and MEM200 and DPU300 having exclusive operation relation are connected to the CPU400 without unnecessary redundancy.
JP55175415A 1980-12-12 1980-12-12 Buffer memory device Pending JPS57100679A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55175415A JPS57100679A (en) 1980-12-12 1980-12-12 Buffer memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55175415A JPS57100679A (en) 1980-12-12 1980-12-12 Buffer memory device

Publications (1)

Publication Number Publication Date
JPS57100679A true JPS57100679A (en) 1982-06-22

Family

ID=15995690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55175415A Pending JPS57100679A (en) 1980-12-12 1980-12-12 Buffer memory device

Country Status (1)

Country Link
JP (1) JPS57100679A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS529495A (en) * 1975-07-12 1977-01-25 Yasumoto Takahashi Coin receiving device of vending machine

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS529495A (en) * 1975-07-12 1977-01-25 Yasumoto Takahashi Coin receiving device of vending machine

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