JPS5753968A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5753968A
JPS5753968A JP55129541A JP12954180A JPS5753968A JP S5753968 A JPS5753968 A JP S5753968A JP 55129541 A JP55129541 A JP 55129541A JP 12954180 A JP12954180 A JP 12954180A JP S5753968 A JPS5753968 A JP S5753968A
Authority
JP
Japan
Prior art keywords
sealing resin
electrostatic charge
organic compound
semiconductive organic
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55129541A
Other languages
Japanese (ja)
Inventor
Yuji Matsubara
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP55129541A priority Critical patent/JPS5753968A/en
Publication of JPS5753968A publication Critical patent/JPS5753968A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PURPOSE:To prevent electrostatic charge caused destruction of a semiconductor by a method wherein the outer surface of sealing resin is covered with a semiconductive organic compound. CONSTITUTION:A film of a semiconductive organic compound that is a mixture of a chlorobenzene solution of polyvinylcarbazole and a chloroform solution of electron attracting SbCl3 is applied to the outer surface of sealing resin and is let to dry, the resultant coat lowering the outer surface volume resistance down to approximately 10<7>-10<12>OMEGA/cm (at room temperature) and preventing electrostatic charge. The mechanism of conductivity of such a semiconductive organic compound being that of electron conduction and therefore not requiring moisture to maintain itself, electrostatic charge can be fully prevented even in places where humidity is extremely low. In addition, the compound being free of ionization, the semiconductor device is not hurt as regards the reliability it enjoys. The whole sealing resin other than its outer surface remaining unchanged, there is no increase in leak between elements and leads.
JP55129541A 1980-09-17 1980-09-17 Semiconductor device Pending JPS5753968A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55129541A JPS5753968A (en) 1980-09-17 1980-09-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55129541A JPS5753968A (en) 1980-09-17 1980-09-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5753968A true JPS5753968A (en) 1982-03-31

Family

ID=15012067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55129541A Pending JPS5753968A (en) 1980-09-17 1980-09-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5753968A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0213014A1 (en) * 1985-07-23 1987-03-04 Fairchild Semiconductor Corporation Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate
US4796080A (en) * 1987-07-23 1989-01-03 Fairchild Camera And Instrument Corporation Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate
JPH0252348U (en) * 1988-10-03 1990-04-16
JPH02106940A (en) * 1988-10-17 1990-04-19 Semiconductor Energy Lab Co Ltd Manufacture of electronic device
US6756670B1 (en) 1988-08-26 2004-06-29 Semiconductor Energy Laboratory Co., Ltd. Electronic device and its manufacturing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0213014A1 (en) * 1985-07-23 1987-03-04 Fairchild Semiconductor Corporation Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate
US4796080A (en) * 1987-07-23 1989-01-03 Fairchild Camera And Instrument Corporation Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate
US6756670B1 (en) 1988-08-26 2004-06-29 Semiconductor Energy Laboratory Co., Ltd. Electronic device and its manufacturing method
JPH0252348U (en) * 1988-10-03 1990-04-16
JPH02106940A (en) * 1988-10-17 1990-04-19 Semiconductor Energy Lab Co Ltd Manufacture of electronic device

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