JPS5746552A - Clock generating circuit of dual system - Google Patents
Clock generating circuit of dual systemInfo
- Publication number
- JPS5746552A JPS5746552A JP55122243A JP12224380A JPS5746552A JP S5746552 A JPS5746552 A JP S5746552A JP 55122243 A JP55122243 A JP 55122243A JP 12224380 A JP12224380 A JP 12224380A JP S5746552 A JPS5746552 A JP S5746552A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- circuit
- switching
- dual system
- generating circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To prevent the no clock state accompanined with the switching operation and set an operation delay time independently even in case of connection of plural stages of clock switching circuits, by adding a clock holding circuit to the clock switching circuit. CONSTITUTION:A clock holding circuit, for examples, tuning circuits 13-N and 13- E which transmit clocks for a constant time even after the break of clocks are added to a clock generating circuit 4 of the dual system. Thus, even if a clock CLK-N is broken, a clock switching circuit 11 receives the clock CLK-N reproduced from the tuning circuit 13-N during the operation delay time to the switching operation after receiving of the control signal of a clock break detector 12-N, and therefore, the clock CLK is not broken.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55122243A JPS5746552A (en) | 1980-09-05 | 1980-09-05 | Clock generating circuit of dual system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55122243A JPS5746552A (en) | 1980-09-05 | 1980-09-05 | Clock generating circuit of dual system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5746552A true JPS5746552A (en) | 1982-03-17 |
Family
ID=14831127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55122243A Pending JPS5746552A (en) | 1980-09-05 | 1980-09-05 | Clock generating circuit of dual system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5746552A (en) |
-
1980
- 1980-09-05 JP JP55122243A patent/JPS5746552A/en active Pending
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