JPS5729167A - Multicomputer system - Google Patents
Multicomputer systemInfo
- Publication number
- JPS5729167A JPS5729167A JP10368480A JP10368480A JPS5729167A JP S5729167 A JPS5729167 A JP S5729167A JP 10368480 A JP10368480 A JP 10368480A JP 10368480 A JP10368480 A JP 10368480A JP S5729167 A JPS5729167 A JP S5729167A
- Authority
- JP
- Japan
- Prior art keywords
- level
- fault
- period
- normal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Abstract
PURPOSE:To prevent data transfer between normal stations from being disabled, by detecting an electronic computer having caused a fault, and disconnecting it from a data line. CONSTITUTION:On inputting a program-run signal PR, a fault detecting circuit 22 judges a normal state when the period Tp is included in a predetermined period, and the output is at a level H. If a fault of processing occurs in a computer 20, however, the period of the program-run signal PR is disordered, so the period longer than the prescribed is regarded as normal one to make the circuit generate an L- level output. When the fault detection results in that the output of the circuit 22 goes down to the level L, a switch curcuit 23 is turned on the disconnect a data line 10 from the device 20, thereby preventing an error signal from being sent out and data transfer between normal stations from being disabled by holding the data line at the level L.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10368480A JPS5729167A (en) | 1980-07-30 | 1980-07-30 | Multicomputer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10368480A JPS5729167A (en) | 1980-07-30 | 1980-07-30 | Multicomputer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5729167A true JPS5729167A (en) | 1982-02-17 |
Family
ID=14360600
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10368480A Pending JPS5729167A (en) | 1980-07-30 | 1980-07-30 | Multicomputer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5729167A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58203533A (en) * | 1982-05-24 | 1983-11-28 | Meidensha Electric Mfg Co Ltd | Data processor |
JPH01209541A (en) * | 1988-02-18 | 1989-08-23 | Oki Electric Ind Co Ltd | Redundant constitution system for information processor |
-
1980
- 1980-07-30 JP JP10368480A patent/JPS5729167A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58203533A (en) * | 1982-05-24 | 1983-11-28 | Meidensha Electric Mfg Co Ltd | Data processor |
JPS6220585B2 (en) * | 1982-05-24 | 1987-05-07 | Meidensha Electric Mfg Co Ltd | |
JPH01209541A (en) * | 1988-02-18 | 1989-08-23 | Oki Electric Ind Co Ltd | Redundant constitution system for information processor |
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