JPS55103617A - Computer system - Google Patents

Computer system

Info

Publication number
JPS55103617A
JPS55103617A JP1045679A JP1045679A JPS55103617A JP S55103617 A JPS55103617 A JP S55103617A JP 1045679 A JP1045679 A JP 1045679A JP 1045679 A JP1045679 A JP 1045679A JP S55103617 A JPS55103617 A JP S55103617A
Authority
JP
Japan
Prior art keywords
circuit
switch
signal
turned
hot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1045679A
Other languages
Japanese (ja)
Inventor
Yukiyoshi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1045679A priority Critical patent/JPS55103617A/en
Publication of JPS55103617A publication Critical patent/JPS55103617A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To change-over a switch at a hot-line insertion and removal time of a print board not only to generate a response false signal in an interface circuit but also to make an alarm detection circuit ineffective.
CONSTITUTION: In case of hot-line insertion and removal of the print board of circuit 2 for I/O device, selector switch 16 is turned on previously. Under the turning- on state, output S1 or OR circuit 13A for alarm circuit becomes a signal, which indicates always a normal operation, due to the signal from switch 16. Response signal generation circuit 14 is operated by I/O device selection signal S3. In case that switch 16 is turned off, NAND circuit 15 is not operated because of the failure of AND conditions. However, in case that switch 16 is turned on, NAND circuit 15 is operated due to the truth of AND conditions. Consequently, even for hot-line insertion and removal of the plug-in of the circuit for I/O device, central processing unit 3 is not stopped because a false response signal can be obtained from interface circuit 1.
COPYRIGHT: (C)1980,JPO&Japio
JP1045679A 1979-02-02 1979-02-02 Computer system Pending JPS55103617A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1045679A JPS55103617A (en) 1979-02-02 1979-02-02 Computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1045679A JPS55103617A (en) 1979-02-02 1979-02-02 Computer system

Publications (1)

Publication Number Publication Date
JPS55103617A true JPS55103617A (en) 1980-08-08

Family

ID=11750637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1045679A Pending JPS55103617A (en) 1979-02-02 1979-02-02 Computer system

Country Status (1)

Country Link
JP (1) JPS55103617A (en)

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