JPS57210741A - Transmission speed converting system for digital data - Google Patents
Transmission speed converting system for digital dataInfo
- Publication number
- JPS57210741A JPS57210741A JP56094029A JP9402981A JPS57210741A JP S57210741 A JPS57210741 A JP S57210741A JP 56094029 A JP56094029 A JP 56094029A JP 9402981 A JP9402981 A JP 9402981A JP S57210741 A JPS57210741 A JP S57210741A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- latch circuit
- data
- converted
- transmission speed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
Abstract
PURPOSE:To perform the conversion of a transmission speed of a digital data with good accuracy. CONSTITUTION:A signal 31 to be converted from a oscillator 30 oscillating the signal to be converted such as a digital audio disc or a tape is applied to a latch circuit 32 and a difference detector 34. In the latch circuit 32, a clock pulse 33 in frequency f1 is applied from the transmitter 30 and a delay data 35 shifted by one phase from the signal 31 is applied to the detector 34. A difference output 37 is multiplied with a coefficient 39 sequentially designated from a multiplication coefficient set counter 38 at a multiplier 36. The result of multiplication 34 is latched to a latch circuit 42 to be an interpolation data 47. The data 47 and the delayed data 35 are added at an addition circuit 46 to be a new converted signal 49. The signal 49 is applied to a latch circuit 48. The latch circuit 48 latches the converted signal 49 inputted by taking a clock pulse 52 in frequency f2 supplied from a receiver 50.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56094029A JPS57210741A (en) | 1981-06-19 | 1981-06-19 | Transmission speed converting system for digital data |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56094029A JPS57210741A (en) | 1981-06-19 | 1981-06-19 | Transmission speed converting system for digital data |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57210741A true JPS57210741A (en) | 1982-12-24 |
Family
ID=14099132
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56094029A Pending JPS57210741A (en) | 1981-06-19 | 1981-06-19 | Transmission speed converting system for digital data |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57210741A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0228646A2 (en) * | 1985-12-20 | 1987-07-15 | Hitachi, Ltd. | A signal processing apparatus for disc memory devices |
-
1981
- 1981-06-19 JP JP56094029A patent/JPS57210741A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0228646A2 (en) * | 1985-12-20 | 1987-07-15 | Hitachi, Ltd. | A signal processing apparatus for disc memory devices |
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