JPS57207902A - Input circuit of controlling device - Google Patents

Input circuit of controlling device

Info

Publication number
JPS57207902A
JPS57207902A JP9426581A JP9426581A JPS57207902A JP S57207902 A JPS57207902 A JP S57207902A JP 9426581 A JP9426581 A JP 9426581A JP 9426581 A JP9426581 A JP 9426581A JP S57207902 A JPS57207902 A JP S57207902A
Authority
JP
Japan
Prior art keywords
circuits
input
gates
outputs
level converting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9426581A
Other languages
Japanese (ja)
Inventor
Ryozo Murakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9426581A priority Critical patent/JPS57207902A/en
Publication of JPS57207902A publication Critical patent/JPS57207902A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/04Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/058Safety, monitoring
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/10Plc systems
    • G05B2219/11Plc I-O input output
    • G05B2219/1176I-O signal processing, adaption, conditioning, conversion of signal levels
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/10Plc systems
    • G05B2219/11Plc I-O input output
    • G05B2219/1181Detection of I-O faults, shut down of I-O

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE:To reduce the number of level converting circuts so as to minimize the size of the device, by installing level converting circuits for detecting abnormality which are commonly used for numerous input contact signals. CONSTITUTION:An input circuit is constituted in such a way that level converting circuits 9 and 10 for detecting abnormality are commonly installed for each signal input contact 1a-1n, and instantaneous inputs of the contacts 1a-1n are inputted into the circuits 9 and 10 through contacts 1a-1n are inputted into the circuits 9 and 10 through diodes 11a-11n for preventing reverse current, and the output of the circuit 9 is made as a common input of comparators 5a-5n, and then, outputs of the circuits 9 and 10 are compared with each other at a comparator 12. The comparator 12 is constituted in such a way that, when the input is different from the proper one, it sets an FF 13 and closes all gates of AND gates 14a-14n equipped with inhibit input which correspond to each contact 1a-1n, respectively. Outputs of level converting circuits 2a-2n and the circuits 5a-5n which correspond to each contact 1a-1n, respectively, and the output of the FF 13 are inputted into the gates 14a-14n. When input signals of the circuits 5a-5n are different from proper ones, the outputs of the of the gates 14a-14n become ''0''. Moreover, when an abnormality is detected at th comparator 12, it is decided that whether the input signal is normal or abnormal by setting the outputs of the gates 14a-14n.
JP9426581A 1981-06-17 1981-06-17 Input circuit of controlling device Pending JPS57207902A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9426581A JPS57207902A (en) 1981-06-17 1981-06-17 Input circuit of controlling device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9426581A JPS57207902A (en) 1981-06-17 1981-06-17 Input circuit of controlling device

Publications (1)

Publication Number Publication Date
JPS57207902A true JPS57207902A (en) 1982-12-20

Family

ID=14105445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9426581A Pending JPS57207902A (en) 1981-06-17 1981-06-17 Input circuit of controlling device

Country Status (1)

Country Link
JP (1) JPS57207902A (en)

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