JPS57168353A - Interruption input failure detecting system - Google Patents
Interruption input failure detecting systemInfo
- Publication number
- JPS57168353A JPS57168353A JP56053037A JP5303781A JPS57168353A JP S57168353 A JPS57168353 A JP S57168353A JP 56053037 A JP56053037 A JP 56053037A JP 5303781 A JP5303781 A JP 5303781A JP S57168353 A JPS57168353 A JP S57168353A
- Authority
- JP
- Japan
- Prior art keywords
- and2
- signal
- circuit and1
- inputted
- fault
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
Abstract
PURPOSE:To obtain a computer which is strong and high in safety, and is capable of quickly coping with without exerting influence on the whole computer system, by detaching a faulty part, in case when a fault has occurred in an interruption signal receiving circuit. CONSTITUTION:When an interrupting signal (factor 1 or 2) is inputted, an FF 1 or an FF 2 is set, said signal is inputted to one of an AND circuit AND1 or AND2, an overflow signal of a counter is applied to the other, and an output of one of them is transferred to an input terminal iRT of a CPU. In this state, in case when a fault, etc. have occurred, the FF 1 or the FF 2 are always turned on, and the terminal iRT of the CPU from the circuit AND1 or AND2 remains turned-on. As a result, only an interruption processing block is executed repeatedly, a counter 1 or 2 overflows, an output of the circuit AND1 or AND2 becomes ''0'', and the processing is always returned to an exeuction program. Accordingly, the factor 1 or 2 is detached from the system.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56053037A JPS57168353A (en) | 1981-04-10 | 1981-04-10 | Interruption input failure detecting system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56053037A JPS57168353A (en) | 1981-04-10 | 1981-04-10 | Interruption input failure detecting system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57168353A true JPS57168353A (en) | 1982-10-16 |
Family
ID=12931679
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56053037A Pending JPS57168353A (en) | 1981-04-10 | 1981-04-10 | Interruption input failure detecting system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57168353A (en) |
-
1981
- 1981-04-10 JP JP56053037A patent/JPS57168353A/en active Pending
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