JPS57202136A - Muting circuit - Google Patents
Muting circuitInfo
- Publication number
- JPS57202136A JPS57202136A JP8694381A JP8694381A JPS57202136A JP S57202136 A JPS57202136 A JP S57202136A JP 8694381 A JP8694381 A JP 8694381A JP 8694381 A JP8694381 A JP 8694381A JP S57202136 A JPS57202136 A JP S57202136A
- Authority
- JP
- Japan
- Prior art keywords
- switch
- terminal
- circuit
- muting
- sensitivity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/34—Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems
Abstract
PURPOSE:To receive a signal with a lower reception level, by switching a characteristic of a frequency selecting circuit to a narrow band for reduction in intermodulation interference and changing over a lower muting sensitivity to lower one at the same time. CONSTITUTION:When a selectivity changeover switch 14 is connected to a terminal (b) side, a frequency selecting circuit 2 has a broad band characteristic, a receiver acts like high sensitivity reception and an output of a level detector 11 having higher detection level is applied to a muting circuit through the terminal (b) side of a muting sensitivity changeover switch 20 functioning cooperatively with a switch. When the circuit 2 is operated at a narrow band by switching the switch 14 to the terminal (a) to reduce intermodulation interference, since the reception sensitivity is also reduced, the switch 20 is also changed over to the terminal (a) side in interlocking with the switch 14, and an output of the level detector 11 with lower detection level is applied to the muting circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8694381A JPS57202136A (en) | 1981-06-08 | 1981-06-08 | Muting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8694381A JPS57202136A (en) | 1981-06-08 | 1981-06-08 | Muting circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57202136A true JPS57202136A (en) | 1982-12-10 |
JPH0151217B2 JPH0151217B2 (en) | 1989-11-02 |
Family
ID=13900947
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8694381A Granted JPS57202136A (en) | 1981-06-08 | 1981-06-08 | Muting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57202136A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100378121B1 (en) * | 1999-12-29 | 2003-03-29 | 삼성전자주식회사 | Intermodulation control device and method in a mobile communication system |
-
1981
- 1981-06-08 JP JP8694381A patent/JPS57202136A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100378121B1 (en) * | 1999-12-29 | 2003-03-29 | 삼성전자주식회사 | Intermodulation control device and method in a mobile communication system |
Also Published As
Publication number | Publication date |
---|---|
JPH0151217B2 (en) | 1989-11-02 |
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