JPS57199252A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS57199252A JPS57199252A JP56085222A JP8522281A JPS57199252A JP S57199252 A JPS57199252 A JP S57199252A JP 56085222 A JP56085222 A JP 56085222A JP 8522281 A JP8522281 A JP 8522281A JP S57199252 A JPS57199252 A JP S57199252A
- Authority
- JP
- Japan
- Prior art keywords
- collector
- layer
- base
- terminals
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
Abstract
PURPOSE:To make gate speed at each output terminal faster and make each speed equal by a method wherein a plurality of collector regios and collector output terminals are laid next to base input terminals on the same line in a base region and a couple of such systems are laid parallel facting each other. CONSTITUTION:A p type base layer 2 of a horizontal type n-p-n transistor of a semiconductor integrated circuit device which composes an integrated injection logic circuit is so arranged to face an emitter p<+> layer 6 of the n-p-n transistor. Then collector regions 1a, 1b and 1c and output terminals 4a, 4b and 4c of a collector region 1 are formed on the base layer 2 in such a manner that those respective regions and terminals are laid parallel to the p<+> layer 6 with respective base input terminals 5a, 5b and 5c in between.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56085222A JPS57199252A (en) | 1981-06-01 | 1981-06-01 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56085222A JPS57199252A (en) | 1981-06-01 | 1981-06-01 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57199252A true JPS57199252A (en) | 1982-12-07 |
Family
ID=13852534
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56085222A Pending JPS57199252A (en) | 1981-06-01 | 1981-06-01 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57199252A (en) |
-
1981
- 1981-06-01 JP JP56085222A patent/JPS57199252A/en active Pending
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