JPS57199043A - Operating device - Google Patents

Operating device

Info

Publication number
JPS57199043A
JPS57199043A JP8539481A JP8539481A JPS57199043A JP S57199043 A JPS57199043 A JP S57199043A JP 8539481 A JP8539481 A JP 8539481A JP 8539481 A JP8539481 A JP 8539481A JP S57199043 A JPS57199043 A JP S57199043A
Authority
JP
Japan
Prior art keywords
carry
circuit
output
significant bit
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8539481A
Other languages
Japanese (ja)
Other versions
JPS622329B2 (en
Inventor
Tomoaki Isozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8539481A priority Critical patent/JPS57199043A/en
Publication of JPS57199043A publication Critical patent/JPS57199043A/en
Publication of JPS622329B2 publication Critical patent/JPS622329B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To output the carry output from an optional bit to an external circuit to execute the operation in two machine cycles, by delaying the carry output from the operating circuit for the most significant bit out of many arranged bits by one machine cycle to input this carry output to the carry input of the operating circuit for the least significant bit. CONSTITUTION:A multi-bits operating device is provided one-bit arithmetic logical operation circuits 31-34, and carry outputs Cn of circuits 31-33 are inputted to carry inputs Ci of circuits 32-34 respectively. A carry output Co of the circuit 34 for the most significant bit is inputted to a delay FF35 for delaying a signal by one machine cycle and a transfer gate 39. The output of this FF35 is inputted to the carry input Ci of the circuit 31 for the least significant bit through a transfer gate 36. The first signal 43 is applied to not only the gate 36 and a transfer gate 38 but also gates 37 and 39 through an inverter 40. Outputs of gates 38 and 39 are applied to a skip circuit 41 which executes the skip instruction, and thus, the operation is executed in two machine cycles.
JP8539481A 1981-06-03 1981-06-03 Operating device Granted JPS57199043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8539481A JPS57199043A (en) 1981-06-03 1981-06-03 Operating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8539481A JPS57199043A (en) 1981-06-03 1981-06-03 Operating device

Publications (2)

Publication Number Publication Date
JPS57199043A true JPS57199043A (en) 1982-12-06
JPS622329B2 JPS622329B2 (en) 1987-01-19

Family

ID=13857548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8539481A Granted JPS57199043A (en) 1981-06-03 1981-06-03 Operating device

Country Status (1)

Country Link
JP (1) JPS57199043A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018116483A1 (en) * 2016-12-21 2018-06-28 和己 阿部 Calculation using numerical values represented inside a computer in undecimal or higher positional notation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5047532A (en) * 1973-08-27 1975-04-28
JPS5563434A (en) * 1978-11-07 1980-05-13 Fujitsu Ltd Adder

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5047532A (en) * 1973-08-27 1975-04-28
JPS5563434A (en) * 1978-11-07 1980-05-13 Fujitsu Ltd Adder

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018116483A1 (en) * 2016-12-21 2018-06-28 和己 阿部 Calculation using numerical values represented inside a computer in undecimal or higher positional notation

Also Published As

Publication number Publication date
JPS622329B2 (en) 1987-01-19

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