JPS6428725A - Floating point arithmetic circuit - Google Patents

Floating point arithmetic circuit

Info

Publication number
JPS6428725A
JPS6428725A JP62183293A JP18329387A JPS6428725A JP S6428725 A JPS6428725 A JP S6428725A JP 62183293 A JP62183293 A JP 62183293A JP 18329387 A JP18329387 A JP 18329387A JP S6428725 A JPS6428725 A JP S6428725A
Authority
JP
Japan
Prior art keywords
function
floating point
operation mode
right shift
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62183293A
Other languages
Japanese (ja)
Other versions
JP2561638B2 (en
Inventor
Koji Imazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62183293A priority Critical patent/JP2561638B2/en
Publication of JPS6428725A publication Critical patent/JPS6428725A/en
Application granted granted Critical
Publication of JP2561638B2 publication Critical patent/JP2561638B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To realize left/right shift of an optional bit by adding a function normalizing the result of arithmetic operation for the circuit and a function stopping the overflow protection function of the output by the designation of a specific operation mode. CONSTITUTION:A function is provided, which stops the function normalizing the result of arithmetic operation and the output overflow protection function through the designation of the specific operation mode to a floating point arithmetic circuit. In the operating mode, a data to be shifted is given to one input and a data whose mantissa part is zero and exponent part corresponds to the shift is supplied to the other input to realize the left/right shift. Then the said operation mode and the data of the mantissa part and the exponent part as a scaling constant are designated by a specific command. Thus, the effect is obtained that the left/right shift of an optional bit is realized by one instruction cycle.
JP62183293A 1987-07-24 1987-07-24 Floating point arithmetic circuit Expired - Lifetime JP2561638B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62183293A JP2561638B2 (en) 1987-07-24 1987-07-24 Floating point arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62183293A JP2561638B2 (en) 1987-07-24 1987-07-24 Floating point arithmetic circuit

Publications (2)

Publication Number Publication Date
JPS6428725A true JPS6428725A (en) 1989-01-31
JP2561638B2 JP2561638B2 (en) 1996-12-11

Family

ID=16133124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62183293A Expired - Lifetime JP2561638B2 (en) 1987-07-24 1987-07-24 Floating point arithmetic circuit

Country Status (1)

Country Link
JP (1) JP2561638B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS581244A (en) * 1981-06-26 1983-01-06 Fujitsu Ltd Detecting method for exception of floating decimal point instruction
JPS60245046A (en) * 1984-05-21 1985-12-04 Fujitsu Ltd Logical shift arithmetic circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS581244A (en) * 1981-06-26 1983-01-06 Fujitsu Ltd Detecting method for exception of floating decimal point instruction
JPS60245046A (en) * 1984-05-21 1985-12-04 Fujitsu Ltd Logical shift arithmetic circuit

Also Published As

Publication number Publication date
JP2561638B2 (en) 1996-12-11

Similar Documents

Publication Publication Date Title
EP0351242A3 (en) Floating point arithmetic units
EP0130380A3 (en) Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system
ATE186131T1 (en) FLOATING POINT PROCESSING UNIT WITH NORMALIZATION
JPS5345939A (en) Ram circuit
EP0130381A3 (en) Mechanism for implementing one machine cycle executable branch-on-any-bit-in-any-register instructions in a primitive instruction set computing system
JPS5484936A (en) Decoder circuit
JPS6428725A (en) Floating point arithmetic circuit
JPS54158830A (en) High-speed arithmetic processing system
JPS57103552A (en) Data processor
JPS56147237A (en) Operation processing device
DE3687778D1 (en) Addierzelle fuer carry-ripple-addierer in cmos-technik.
JPS54112134A (en) Logical operation circuit
JPS5318803A (en) Duplex pump
JPS5748141A (en) Address conversion system
JPS5690343A (en) Data normalization device
JPS5685157A (en) Information processor
JPS5730033A (en) Data processor
JPS5729149A (en) Decimal arithmetic system
KR920020850A (en) Floating point multiplier
JPS54159832A (en) Adder and subtractor for numbers different in data length
JPS57161940A (en) Central processing device
JPS57136254A (en) Arithmetic processor
EP0150275A3 (en) Circuit arrangement for the generation of check bits
JPS57196350A (en) Data processor
JPS538031A (en) Address setting system