JP2561638B2 - Floating point arithmetic circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating point arithmetic circuit, for example, a digital digital processor having a floating point arithmetic circuit or a microcomputer system including the floating point arithmetic circuit. It relates to effective technology.

[Conventional technology]

For the floating-point arithmetic circuit, see, for example, “Nikkei Electronics”, Nikkei McGraw-Hill, Inc., August 25, 1986.
There are pages 201 to 209.

[Problems to be solved by the invention]

In the floating point arithmetic circuit, the number representation is performed by the mantissa part and the exponent part. From this, when one of the two data has a mantissa of zero and constant data is supplied to the exponent, the shift operation can be performed according to the difference between the exponents. However, the floating-point arithmetic circuit is provided with a protection circuit because overflow or underflow of the exponent causes many problems in the calculation of the output of the mantissa in the normal floating-point arithmetic operation. Therefore, even if the above method is used, for example, in the case of data whose mantissa part is 16 bits, right shift is limited to 15 bits and left shift is fixed to the maximum value.

An object of the present invention is to provide a floating point arithmetic circuit having a high speed shift function.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is,
The floating point arithmetic circuit is provided with a function of normalizing the arithmetic result and a function of stopping the output overflow protection function by designating a specific operation mode.

[Work]

According to the above-mentioned means, it is possible to realize the left-right shift operation of any bit by utilizing the arithmetic operation of the exponent part in the above operation mode.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a floating point arithmetic circuit according to the present invention. Although not particularly limited, each circuit block shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

Although not particularly limited, a signal supplied through one of the data buses XorY-BUS, which transmits 20 bits of data expressed by a 16-bit mantissa part and a 4-bit exponent part, is a selector 1 and an exponent part. Comparison circuit 9
Is supplied to one input of each. Similarly to the above, the signal supplied through the other data bus D-BUS, which transmits the data of 20 bits in total expressed by the mantissa part consisting of 16 bits and the exponent part consisting of 4 bits, is the selector 1 and the exponent part comparison circuit. 9 to the other input, respectively.

The exponent part comparison circuit 9 compares the exponent part eA of both data with the exponent part eA.
By comparing with eB, the selector 1 is controlled so that the exponent part having a smaller value is transmitted to the right shifter 2. For example, the exponent part of the data supplied from the data bus XorY-BUS is e
In A, it is assumed that the exponent part of the data supplied from the data bus D-BUS is eB, and if eA> eB, the selector 1 outputs the data of the mantissa part crosswise, and if eA <eB,
The selector 1 outputs the mantissa data as it is. As a result, the mantissa part data corresponding to the smaller exponent part is always supplied to the right shifter 2 side.

In the right shifter 2, the difference formed by the exponent part comparison circuit 9, in other words, the subtracted shift amount.
| eA−eB | is supplied. As a result, the data of the mantissa part having the smaller exponent part is shifted to the right by a bit corresponding to the shift amount | eA−eB |. As a result, the exponent part of both data is adjusted to the larger one.

Since the data bits of the mantissa part are matched by the above data operation, the fixed arithmetic logic operation unit (hereinafter, simply
The addition / subtraction is executed by ALU 3.

The output signal of the ALU3 is input to the left shifter 6. The left shifter 6 is used to normalize the calculation result (mantissa part) of the ALU3. That is, the output signal of the ALU 3 is also input to the 0.1 detection circuit 4, where the number of 1s or 0s below the decimal point is counted, and the shift operation of the left shifter 6 is performed by the counted number. That is, when the operation result is a positive value, the left shifter 6 shifts the data of the mantissa part of the operation result until the first place after the decimal point is 1, and when it is a negative value, it becomes 0.

The operation result of the mantissa part normalized by the left shifter 6 is supplied to the mantissa part of the accumulator 8 through the overflow protection circuit 7. Overflow protection circuit 7
Prohibits overflow output of the above calculation result. That is, even if an overflow occurs in the above calculation result, it has a function of fixing the effect to the maximum value. Such an overflow protection function prevents an infinite operand from occurring and stopping the entire operation sequence.

The exponent part addition / subtraction circuit 10 performs addition / subtraction of the exponent parts eA and eB and supplies the result to the exponent part of the accumulator 8. The calculation result held in the accumulator 8 is recalculated or stored in a predetermined storage circuit through the data bus D-BUS.

In this embodiment, the following circuit is added in order to realize the high speed shift function by the floating point arithmetic circuit. Although not particularly limited, the shift mode signal SFM is determined by the designation of a specific operation mode. The signal SFM is set to low level (logic "0") in the normal floating point operation mode, and is set to high level (logic "1") in the shift mode.

On the one hand, this signal SFM controls the switching of the newly provided selector 5. The output signal of the 0.1 detection circuit 4 is supplied to one input of the selector 5.
The other input of the selector 5 is supplied with the shift amount | eA−eB | formed by the exponential part comparison circuit. When the signal SFM is at low level, the selector 5 detects the 0.1 detection circuit 4 described above.
To the left shifter 6. As a result, the operation result is normalized as described above. The selector 5 is
When the signal SFM is at high level, the shift amount | eA-eB | is transmitted to the left shifter 6. As a result, a left shift operation as will be described later is realized.

On the other hand, the signal SFM is supplied to the overflow protection circuit 7. The operation of the overflow protection circuit 7 is invalidated when the signal SFM is at a high level, in other words, in the shift operation mode. That is,
The overflow protection circuit 7 transmits the input signal (the output signal of the left shifter 7) as it is to the accumulator 8 when the signal SFM is at the high level.

(1) The right shift operation is performed as follows.

For example, the mantissa value of the data to be shifted is 0.100.
[0101] In 1010, it is assumed that the exponent part (eA) is 0001. When this is shifted to the right by 5 bits, the mantissa is 0.000 0000 0000 0000 (zero) as the other data.
And the exponent part (eB) is set to 0110 corresponding to the 5-bit shift amount.

In this case, the value of exponent eA is small, so selector 1
Supplies the mantissa part of the data to be shifted to the right shifter 2. The right shifter 2 shifts to the right by the difference eB-eA (decimal 6-1 = 5) of the exponent part. As a result, the mantissa data output through the right shifter 2 is
0.000 0010 0010 1000 becomes, and bits more than LSB, 0110
Is truncated.

On the other hand, the data of ALU3 is zero (0.000 0000 0
000 0000), the above right-shifted data is output as it is.

In the shift operation mode as described above, the above signal SFM
The output of the 0.1 detection circuit 4 is invalidated by the high level of, and the normalization by the left shifter 6 is not performed, and when eA is small as described above, the difference becomes a negative value. Shift is disabled, above ALU3
The output of is transmitted as it is. The exponent comparison circuit 9
In the above, the shift amount supplied to the selector 5 may be set to 0 under the above condition due to the magnitude relationship between the exponents eA and eB.

Further, since the operation of the overflow protection circuit 7 is prohibited by the high level of the signal SFM, the accumulator 8 stores the data of the mantissa part formed by the right shifter 2. The index part is 0001 as it is
Is stored. That is, at this time, the operation of the exponent addition / subtraction circuit is also invalidated. It should be noted that disabling the operation of the overflow protection circuit 7 has no substantial meaning because an overflow cannot occur in the right shift operation.

(2) The left shift operation is performed as follows.

For example, the mantissa value of the data to be shifted is 0.100.
[0101] In 1010, the exponent part (eA) is 0110. When shifting this to the left by 5 bits, the mantissa part is 0.000 0000 0000 0000 (zero) as the other data.
, And sets the exponent part (eB) to 0001 corresponding to the 5-bit shift amount.

In this case, the value of exponent eB is small, so selector 1
Tells the ALU the mantissa part of the data to be shifted.
Since the zero data is stored in the right shifter 2 and its shift operation is meaningless, the operation of the right shifter 2 may be prohibited when eA-eB takes a positive value.

Therefore, the above data is 0.100 01 from the output of ALU3.
01 0010 1010 is output as is. However, when eA-eB takes a positive value as described above, the selector 5 notifies the left shifter 6 as an effective shift amount, so that the left shifter 6
It shifts to the left by the difference eB-eA (6-1 = 5 in decimal) of the exponent part. As a result, the data of the mantissa part output through the left shifter 6 becomes 1.010 0011 0100 0000, and overflow occurs. However, depending on the high level of the signal SFM, the overflow protection circuit 7
Since the above operation is prohibited, the data of the mantissa part formed by the left shifter 6 is stored in the accumulator 8. At this time, the MSB (sign bit) is 1, and the format is such that it represents a negative number. However, since this operation mode is a data shift operation mode, it is treated as a simple bit operation, so there is no problem. .

In this embodiment, the mantissa is zero, and the shift operation by the floating-point arithmetic circuit can be performed by supplying the value of exponent eB (scaling constant). By designating the shift operation and the scaling constant with a specific command, it is possible to realize the shift of any bit on the left and right of the data in one instruction cycle. As a result, in performing a multi-bit shift operation as in the related art, it is possible to realize a higher-speed shift operation as compared with the case where a 1-bit shift cycle is executed multiple times.

The operation and effect obtained from the above embodiment is as follows. That is, (1) a function for normalizing the operation result and a function for protecting the overflow of the output are added to the floating-point arithmetic circuit by the function of designating a specific operation mode, and one input is shifted in that operation mode. By supplying power data and supplying the other input with data whose mantissa part is zero and whose exponent part corresponds to the shift amount, it is possible to realize the left-right shift operation.

(2) The operation mode, the mantissa part as a scaling constant, and the exponent part data are specified by a specific command. As a result, it is possible to achieve an effect that an arbitrary bit can be shifted left and right in one instruction cycle.

(3) With the above (1) and (2), it is possible to obtain the effect that the floating-point arithmetic circuit can be made multifunctional.

Although the invention made by the inventor of the present application has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment and various modifications can be made without departing from the scope of the invention. Nor. For example, in the shift operation mode, the operation of selectively performing the operation of the right shifter and the operation of the left shifter may be performed according to a command for right shift and a command for left shift. Also,
The shift amount may be such that the shift amount is added to or subtracted from the exponent part of the data to be shifted to generate the exponent eA inside the exponent comparison circuit or the like. As described above, various embodiments can be adopted as the method of operating the right shifter and the left shifter in a substantially alternate manner according to the shift direction.

The present invention includes a floating point arithmetic circuit such as a digital signal processor or a coprocessor,
Alternatively, it can be widely used in the floating point arithmetic circuit itself.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a function for normalizing the operation result and an output overflow protection function for the floating-point operation circuit are added by a function for stopping the operation by designating a specific operation mode.
In the operation mode, the data to be shifted is supplied to one input, and the data corresponding to the shift amount is supplied to the other input with the mantissa part being zero and the exponent part, whereby the left-right shift operation can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a floating point arithmetic circuit according to the present invention. 1,5 …… Selector, 2 …… Right shifter, ALU …… Fixed arithmetic logic operation unit, 4 …… 0.1 detection circuit, 6 …… Left shifter, 7 …… Overflow protection circuit, 8 …… Accumulator, 9 …… Exponent part comparison circuit, 10 ... Exponent part addition / subtraction circuit

Claims (1)

(57) [Claims] 1. An exponent part comparison circuit for detecting a size comparison and a difference between exponent parts of two input data consisting of a mantissa part and an exponent part; and a size comparison output of the exponent part comparison circuit for controlling the above-mentioned 2 Of the two input data, a first selector that transmits the addend of the input data with the larger exponent to the first output side and the addend of the input data with the smaller exponent to the second output A right shifter for shifting the addend part of the input data output from the second output side of the first selector according to the difference output of the exponential part comparison circuit; and the first output of the first selector. A fixed arithmetic operation unit that receives the addend part of the input data output from the side and the addend part of the input data output from the right shifter, and a 0.1 detection circuit that receives the output signal of the fixed arithmetic operation unit, Fixed arithmetic operation above In response to the door of the output signal, above 0.
1 Floating-point arithmetic circuit including a left shifter controlled by the detection signal of the detection circuit and an overflow protection circuit that receives the output signal of the left shifter, detects the overflow, and fixes the result to the maximum value when the overflow occurs In, a shift mode signal and a second selector are added, and when the shift mode signal is enabled, one of the two input data is data to be shifted and the other input data is Let the mantissa part of be zero,
The exponent part of the other input data is set to the difference from the exponent part of the data to be shifted, and the second mode is set when the shift mode signal is valid.
Of the overflow control circuit by switching the control signal input to the left shifter to the differential output of the exponential part comparison circuit in place of the detection signal of the 0.1 detection circuit, and invalidating the operation of the overflow protection circuit by the shift mode signal. Floating point arithmetic circuit characterized by outputting the input signal as it is.