JPS57196337A - Process input and output device - Google Patents

Process input and output device

Info

Publication number
JPS57196337A
JPS57196337A JP56080360A JP8036081A JPS57196337A JP S57196337 A JPS57196337 A JP S57196337A JP 56080360 A JP56080360 A JP 56080360A JP 8036081 A JP8036081 A JP 8036081A JP S57196337 A JPS57196337 A JP S57196337A
Authority
JP
Japan
Prior art keywords
output
input
bus
data
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56080360A
Other languages
Japanese (ja)
Inventor
Akio Otani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56080360A priority Critical patent/JPS57196337A/en
Publication of JPS57196337A publication Critical patent/JPS57196337A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287—Multiplexed DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE:To reduce the load of a computer and to realize a high-speed process for a complex calculation system, by allotting the process input/output bus to plural computers in a time shared way to exclude a bus switch. CONSTITUTION:A direct memory access-interface control DMA-CNT circut 214A performs the input/output of the data between a memory 123A of an A-system computer 12A and the input/output boards 1111-111n in the first half part of each cycle. While a DMA-CNT circuit 214B performs the input/output of the data between a memory 123B of a B-system computer 12B and the boards 1111- 111n in the latter half of each cycle. A process input/output PIO bus 112 is used in a time shared way by the computers 12A and 12B in the first half and the latter half of a cycle respectively. Thus the CPU122A and 122B can perform a cross call without monitoring the state of connection of a bus 112, exclusively by starting the circuits 214A and 214B at an optional time point for the input/ output of the data.
JP56080360A 1981-05-27 1981-05-27 Process input and output device Pending JPS57196337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56080360A JPS57196337A (en) 1981-05-27 1981-05-27 Process input and output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56080360A JPS57196337A (en) 1981-05-27 1981-05-27 Process input and output device

Publications (1)

Publication Number Publication Date
JPS57196337A true JPS57196337A (en) 1982-12-02

Family

ID=13716082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56080360A Pending JPS57196337A (en) 1981-05-27 1981-05-27 Process input and output device

Country Status (1)

Country Link
JP (1) JPS57196337A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4700792A (en) * 1985-05-15 1987-10-20 Tokyo Electric Co., Ltd. Indication method in balance with item indicator
JP2013235300A (en) * 2012-03-26 2013-11-21 Fanuc Ltd Safety signal processing system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4700792A (en) * 1985-05-15 1987-10-20 Tokyo Electric Co., Ltd. Indication method in balance with item indicator
JP2013235300A (en) * 2012-03-26 2013-11-21 Fanuc Ltd Safety signal processing system

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