JPS54130844A - Bus control system - Google Patents

Bus control system

Info

Publication number
JPS54130844A
JPS54130844A JP3814778A JP3814778A JPS54130844A JP S54130844 A JPS54130844 A JP S54130844A JP 3814778 A JP3814778 A JP 3814778A JP 3814778 A JP3814778 A JP 3814778A JP S54130844 A JPS54130844 A JP S54130844A
Authority
JP
Japan
Prior art keywords
bus
control unit
unit
master
directions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3814778A
Other languages
Japanese (ja)
Inventor
Takashi Rokutanda
Yukio Shiraokawa
Keizo Aoyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3814778A priority Critical patent/JPS54130844A/en
Publication of JPS54130844A publication Critical patent/JPS54130844A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To improve the system throughput by performing the operation execution dependent upon an arithmetic control unit and I/O memory operations in parallel.
CONSTITUTION: Main memory 24, arithmetic control unit 26 and a part of plural input devices IO are connected commonly, and information is transferred in both directions by H bus 22 on a basis of the master-slave relation between two arbitrary units connected commonly, and the L bus is controlled by control unit 26 in both directions. Here, when one unit, which is assigned as a slave, of units connected to the H bus has been operating already and cannot answer, a reject signal is transmitted to a master unit, and the master unit releases the H bus and starts the next processing continuously. As a result, the system throughput can be improved by performing the operation execution dependent upon control unit 26 and I/O memory operations in parallel.
COPYRIGHT: (C)1979,JPO&Japio
JP3814778A 1978-04-03 1978-04-03 Bus control system Pending JPS54130844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3814778A JPS54130844A (en) 1978-04-03 1978-04-03 Bus control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3814778A JPS54130844A (en) 1978-04-03 1978-04-03 Bus control system

Publications (1)

Publication Number Publication Date
JPS54130844A true JPS54130844A (en) 1979-10-11

Family

ID=12517299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3814778A Pending JPS54130844A (en) 1978-04-03 1978-04-03 Bus control system

Country Status (1)

Country Link
JP (1) JPS54130844A (en)

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