JPS57193054A - Substrate bias generating circuit - Google Patents

Substrate bias generating circuit

Info

Publication number
JPS57193054A
JPS57193054A JP56077652A JP7765281A JPS57193054A JP S57193054 A JPS57193054 A JP S57193054A JP 56077652 A JP56077652 A JP 56077652A JP 7765281 A JP7765281 A JP 7765281A JP S57193054 A JPS57193054 A JP S57193054A
Authority
JP
Japan
Prior art keywords
substrate
diode
layer
voltage
injected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56077652A
Other languages
Japanese (ja)
Other versions
JPH0423427B2 (en
Inventor
Atsushi Oritani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56077652A priority Critical patent/JPS57193054A/en
Publication of JPS57193054A publication Critical patent/JPS57193054A/en
Publication of JPH0423427B2 publication Critical patent/JPH0423427B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
    • H01L27/0222—Charge pumping, substrate bias generation structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the erroneous operation and improper operation of other circuit of a substrate by absorbing a carrier injected from the anode of a clamping diode provided in a substrate into the substrate by a diode connected to the anode. CONSTITUTION:When the output of an oscillator 10 shifts from low to high level, a voltage at a point A is raised through a capacitor 11, but an N-channel MOS diode 13 is operated, a diode 14 is interrupted while clamping it at the prescribed voltage, and the mobility of charge to the substrate 12 is prevented. When the point A shifts to negative, the region between the N<+> type drain 15 of the diode 13 and the P type substrate 12 is biased forwardly, but a P<++> type layer 16 is bonded to the layer 15, and since the diffusion voltage is lower than the P-N<+> junction, electrons are injected through P<++>-N<+>junction to the layer 16. In this manner, the charge of the substrate is efficiently pumped, the substrate 12 is maintained at the desired bias voltage, and no carrier is injected to the other diffused layer of the substrate. Accordingly, erroneous operation and improper operation can be prevented.
JP56077652A 1981-05-22 1981-05-22 Substrate bias generating circuit Granted JPS57193054A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56077652A JPS57193054A (en) 1981-05-22 1981-05-22 Substrate bias generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56077652A JPS57193054A (en) 1981-05-22 1981-05-22 Substrate bias generating circuit

Publications (2)

Publication Number Publication Date
JPS57193054A true JPS57193054A (en) 1982-11-27
JPH0423427B2 JPH0423427B2 (en) 1992-04-22

Family

ID=13639817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56077652A Granted JPS57193054A (en) 1981-05-22 1981-05-22 Substrate bias generating circuit

Country Status (1)

Country Link
JP (1) JPS57193054A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63307771A (en) * 1987-05-29 1988-12-15 フィリップス　エレクトロニクス　ネムローゼ　フェンノートシャップ Complementary metal oxide semiconductor integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5559757A (en) * 1978-10-30 1980-05-06 Fujitsu Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5559757A (en) * 1978-10-30 1980-05-06 Fujitsu Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63307771A (en) * 1987-05-29 1988-12-15 フィリップス　エレクトロニクス　ネムローゼ　フェンノートシャップ Complementary metal oxide semiconductor integrated circuit

Also Published As

Publication number Publication date
JPH0423427B2 (en) 1992-04-22

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