JPS57184246A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57184246A
JPS57184246A JP56069839A JP6983981A JPS57184246A JP S57184246 A JPS57184246 A JP S57184246A JP 56069839 A JP56069839 A JP 56069839A JP 6983981 A JP6983981 A JP 6983981A JP S57184246 A JPS57184246 A JP S57184246A
Authority
JP
Japan
Prior art keywords
base body
onto
blocks
mounting
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56069839A
Other languages
Japanese (ja)
Inventor
Shigeaki Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP56069839A priority Critical patent/JPS57184246A/en
Publication of JPS57184246A publication Critical patent/JPS57184246A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To increase density, and to miniaturize the device by forming a block having one function by mounting and connecting a semiconductor element, a chip resistor, a chip capacitor and a thick film resistor onto a base body, laminating a plurality of the blocks and working the blocks as a whole. CONSTITUTION:The partial function block 1 formed by mounting and connecting an electronic element chip 5a onto the base body 4a through wires 6 and conductive films 7 and the partial function block 2 formed by mounting and connecting an electronic element chip 5b onto the base body 4b are manufactured, and these blocks are laminated and shaped onto a terminal base 3 to which conn ecting pins 8 are set up. Each block 1, 2 is conducted electrically by one part of the base body 4a and pads 9 for conduction penetrating the base body 4b, and the pads 9 are conducted with the connecting pins 8. Accordingly, not only the density of the device is increased and the device is miniaturized but also the device is easily combined with an optical fiber and parts such as a lens.
JP56069839A 1981-05-08 1981-05-08 Semiconductor device Pending JPS57184246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56069839A JPS57184246A (en) 1981-05-08 1981-05-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56069839A JPS57184246A (en) 1981-05-08 1981-05-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57184246A true JPS57184246A (en) 1982-11-12

Family

ID=13414365

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56069839A Pending JPS57184246A (en) 1981-05-08 1981-05-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57184246A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63500692A (en) * 1985-08-27 1988-03-10 ヒユ−ズ・エアクラフト・カンパニ− Ultra-small electronic package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63500692A (en) * 1985-08-27 1988-03-10 ヒユ−ズ・エアクラフト・カンパニ− Ultra-small electronic package
JPH0324067B2 (en) * 1985-08-27 1991-04-02 Hughes Aircraft Co

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