JPS5718081A - Mos dynamic memory - Google Patents

Mos dynamic memory

Info

Publication number
JPS5718081A
JPS5718081A JP9346080A JP9346080A JPS5718081A JP S5718081 A JPS5718081 A JP S5718081A JP 9346080 A JP9346080 A JP 9346080A JP 9346080 A JP9346080 A JP 9346080A JP S5718081 A JPS5718081 A JP S5718081A
Authority
JP
Japan
Prior art keywords
line signal
time
low level
signal
high level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9346080A
Other languages
Japanese (ja)
Other versions
JPS6135630B2 (en
Inventor
Kazuyasu Fujishima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9346080A priority Critical patent/JPS5718081A/en
Publication of JPS5718081A publication Critical patent/JPS5718081A/en
Publication of JPS6135630B2 publication Critical patent/JPS6135630B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To increase the amount of storage charge, by applying a storage line signal in which it becomes low level after the word line signal is at high level and it becomes high level before it is at low level, to the gate of an MOS capacitor. CONSTITUTION:A bit line receives a signal charge at time t1 and it is set to an equal voltage at both sides of a sense circuit. At time t2, the word line signal is set at high level and a storage line signal S is set at low level, a singl charge 10 is transmitted to the bit line and a change on the bit line signal BL is caused through the presence or absense of the signal charge. The sensing by the sense circuit is made at time t2 and time t3, ant the bit line potential is set at high or low level according to the information. At time t4, the word line signal T remains at high level and the storage line signal S is brought to a high level. At time t5, since the word line signal T is brought to a low level, the information is fetched to the memory cell.
JP9346080A 1980-07-07 1980-07-07 Mos dynamic memory Granted JPS5718081A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9346080A JPS5718081A (en) 1980-07-07 1980-07-07 Mos dynamic memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9346080A JPS5718081A (en) 1980-07-07 1980-07-07 Mos dynamic memory

Publications (2)

Publication Number Publication Date
JPS5718081A true JPS5718081A (en) 1982-01-29
JPS6135630B2 JPS6135630B2 (en) 1986-08-14

Family

ID=14082937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9346080A Granted JPS5718081A (en) 1980-07-07 1980-07-07 Mos dynamic memory

Country Status (1)

Country Link
JP (1) JPS5718081A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0443183Y2 (en) * 1988-04-06 1992-10-13

Also Published As

Publication number Publication date
JPS6135630B2 (en) 1986-08-14

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