JPS57171828A - Analog-to-digital converter - Google Patents
Analog-to-digital converterInfo
- Publication number
- JPS57171828A JPS57171828A JP5757181A JP5757181A JPS57171828A JP S57171828 A JPS57171828 A JP S57171828A JP 5757181 A JP5757181 A JP 5757181A JP 5757181 A JP5757181 A JP 5757181A JP S57171828 A JPS57171828 A JP S57171828A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- counter
- gate
- counting
- digit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To prevent flickering in case of display, by converting digital signals of plural bits which have been A/D-converted, to series pulses of the corresponding number, counting them, and displaying a means value obtained by executing the conversion 10 times. CONSTITUTION:When the first command signal STC is inputted to an A/D converter 11, an analog input signal is A/D-converted, corresponding digital signals b1-bn are outputted, are inputted to a counter 12 by a conversion end signal EOC, simultaneously a gate 14 is opened, a clock pulse CLK is supplied to a down-counter 12, and when a borrow signal BR rises, a clock pulse Ps is supplied to counters 191-194 through a gate 16. When the counter 12 executes down-counting and becomes ''0'', the borrow signal is gone and the gate 16 is closed. When said converting and counting operations are executed 10 times, contents of a counter 19 are transferred to a latch 20 by a signal TRF, and subsequently, as for a numerical value of each digit, upper 3 digits are displayed on a display device 24 by a signal except the lowest digit signal T4 of digit signals T1-T4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5757181A JPS57171828A (en) | 1981-04-16 | 1981-04-16 | Analog-to-digital converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5757181A JPS57171828A (en) | 1981-04-16 | 1981-04-16 | Analog-to-digital converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57171828A true JPS57171828A (en) | 1982-10-22 |
Family
ID=13059524
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5757181A Pending JPS57171828A (en) | 1981-04-16 | 1981-04-16 | Analog-to-digital converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57171828A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009040409A (en) * | 2008-09-08 | 2009-02-26 | Iseki & Co Ltd | Speed control unit for continuously variable transmission for working vehicle |
-
1981
- 1981-04-16 JP JP5757181A patent/JPS57171828A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009040409A (en) * | 2008-09-08 | 2009-02-26 | Iseki & Co Ltd | Speed control unit for continuously variable transmission for working vehicle |
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