JPS5717131A - Retaining device for semiconductor wafer - Google Patents

Retaining device for semiconductor wafer

Info

Publication number
JPS5717131A
JPS5717131A JP9056380A JP9056380A JPS5717131A JP S5717131 A JPS5717131 A JP S5717131A JP 9056380 A JP9056380 A JP 9056380A JP 9056380 A JP9056380 A JP 9056380A JP S5717131 A JPS5717131 A JP S5717131A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
wafer
feeding
retaining base
directions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9056380A
Other languages
Japanese (ja)
Inventor
Ryuichi Funatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9056380A priority Critical patent/JPS5717131A/en
Publication of JPS5717131A publication Critical patent/JPS5717131A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To perform the position matching highly accurately for the subject semiconductor wafer by a method wherein a pneumatic bearing is provided on the retaining base, on which the semiconductor wafer is retained on its upper surface and a spherical base and a driven stick are provided on the lower surface, in such a manner that the above can be moved in vertical direction and rocked in two directions of orthogonal intersection. CONSTITUTION:The spherical bases 14' and 16' are provided on the lower surface of the wafer retaining base 14 which retains the semiconductor wafer 1, the driven stick 15 to be connected to a block 17 is provided, the retaining base 14 is supported on a vertically moving block 16 by feeding positive-pressured air through a tube 23, the rocking in the directions of an X-shaft and a Y-shaft is enabled by feeding air from tubes 18-22 and, and at the same time, a position matching is performed using a pulse motor 4, gears 5, 7 and a feeding screw 8 in such manner that the vertically moving block 16 is moved up and down. Through these procedures, a highly accurate positioning can be performed within the focus depth of the image formation of mask pattern without having the wafer surface to come in contact with other substances.
JP9056380A 1980-07-04 1980-07-04 Retaining device for semiconductor wafer Pending JPS5717131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9056380A JPS5717131A (en) 1980-07-04 1980-07-04 Retaining device for semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9056380A JPS5717131A (en) 1980-07-04 1980-07-04 Retaining device for semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS5717131A true JPS5717131A (en) 1982-01-28

Family

ID=14001886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9056380A Pending JPS5717131A (en) 1980-07-04 1980-07-04 Retaining device for semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS5717131A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165523A (en) * 2004-11-02 2006-06-22 Nikon Corp Stage device having measuring system, initializing, vibration compensating, low-propagating and lightweight precision stage
JP2008519456A (en) * 2004-11-04 2008-06-05 株式会社ニコン Z support device for precision stage
JP2009260137A (en) * 2008-04-18 2009-11-05 Nikon Corp Semiconductor substrate bonding device
JP2009260138A (en) * 2008-04-18 2009-11-05 Sumitomo Heavy Ind Ltd Stage device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165523A (en) * 2004-11-02 2006-06-22 Nikon Corp Stage device having measuring system, initializing, vibration compensating, low-propagating and lightweight precision stage
JP2008519456A (en) * 2004-11-04 2008-06-05 株式会社ニコン Z support device for precision stage
JP2009260137A (en) * 2008-04-18 2009-11-05 Nikon Corp Semiconductor substrate bonding device
JP2009260138A (en) * 2008-04-18 2009-11-05 Sumitomo Heavy Ind Ltd Stage device

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