JPS5726434A - Wafer target pattern for alignment - Google Patents

Wafer target pattern for alignment

Info

Publication number
JPS5726434A
JPS5726434A JP9996380A JP9996380A JPS5726434A JP S5726434 A JPS5726434 A JP S5726434A JP 9996380 A JP9996380 A JP 9996380A JP 9996380 A JP9996380 A JP 9996380A JP S5726434 A JPS5726434 A JP S5726434A
Authority
JP
Japan
Prior art keywords
wafer
target pattern
pattern
window
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9996380A
Other languages
Japanese (ja)
Inventor
Tamotsu Shimizu
Minoru Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9996380A priority Critical patent/JPS5726434A/en
Publication of JPS5726434A publication Critical patent/JPS5726434A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Abstract

PURPOSE:To precisely position a wafer target pattern for alignment by providing the pattern with parallel rectilinear line group of more than 4 lines spaced at different intervals. CONSTITUTION:A target pattern of square window responsive to the visual field of a microscope is drawn on a mask 9, and a target pattern of base matrix is sequentially drawn from right to left and from upside to downside with expanded pitch on the entire aligning range of the wafer. The size of the window is so selected as to include at least two rectilinear line pattens. At this time it is known that the part of the wafer pattern region is located in the visual field at present from the intervals lx, ly of the target pattern in the window 10. Further, the quantity to be moved at the center of the wafer target pattern out of the visual field to the center of the mask target can be also obtained from the relative distances X, Y of the window side and the wafer target pattern, and the mask and the wafer can be precisely matched, and the operation can be facilitated.
JP9996380A 1980-07-23 1980-07-23 Wafer target pattern for alignment Pending JPS5726434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9996380A JPS5726434A (en) 1980-07-23 1980-07-23 Wafer target pattern for alignment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9996380A JPS5726434A (en) 1980-07-23 1980-07-23 Wafer target pattern for alignment

Publications (1)

Publication Number Publication Date
JPS5726434A true JPS5726434A (en) 1982-02-12

Family

ID=14261323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9996380A Pending JPS5726434A (en) 1980-07-23 1980-07-23 Wafer target pattern for alignment

Country Status (1)

Country Link
JP (1) JPS5726434A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999004417A1 (en) * 1997-07-14 1999-01-28 Nikon Corporation Position sensing method and position sensor
US6841890B2 (en) 2002-04-12 2005-01-11 Nec Electronics Corporation Wafer alignment mark for image processing including rectangular patterns, image processing alignment method and method of manufacturing semiconductor device
US7751047B2 (en) * 2005-08-02 2010-07-06 Asml Netherlands B.V. Alignment and alignment marks

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999004417A1 (en) * 1997-07-14 1999-01-28 Nikon Corporation Position sensing method and position sensor
US6841890B2 (en) 2002-04-12 2005-01-11 Nec Electronics Corporation Wafer alignment mark for image processing including rectangular patterns, image processing alignment method and method of manufacturing semiconductor device
US7271906B2 (en) 2002-04-12 2007-09-18 Nec Electronics Corporation Image processing alignment method and method of manufacturing semiconductor device
US7894660B2 (en) 2002-04-12 2011-02-22 Renesas Electronics Corporation Image processing alignment method and method of manufacturing semiconductor device
US7751047B2 (en) * 2005-08-02 2010-07-06 Asml Netherlands B.V. Alignment and alignment marks

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