JPS57169846A - Logic system - Google Patents

Logic system

Info

Publication number
JPS57169846A
JPS57169846A JP56055001A JP5500181A JPS57169846A JP S57169846 A JPS57169846 A JP S57169846A JP 56055001 A JP56055001 A JP 56055001A JP 5500181 A JP5500181 A JP 5500181A JP S57169846 A JPS57169846 A JP S57169846A
Authority
JP
Japan
Prior art keywords
shift register
actuated
register channel
auxiliary
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56055001A
Other languages
Japanese (ja)
Inventor
Susumu Nitta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56055001A priority Critical patent/JPS57169846A/en
Publication of JPS57169846A publication Critical patent/JPS57169846A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To decrease the number of additional auxiliary latched down to a half, by setting an auxiliary latch with every 2nd system latch and connecting the auxiliary latch to every 2nd system latch to form the channels of two types of shift registers. CONSTITUTION:The inputs and outputs are connected to each other among system latches L1-L8 to form a shift register channel. In addition to this 1st shift register channel, the 2nd shift register channel of L1-T1-L3-T2-L5-T3-L7 is formed with auxiliary latches T1, T2 and T3. When a gate signal G1 is actuated, the 1st shift register channel of L1-L2-L3-L4-L5-L6-L7-L8 is actuated. Then a gate G2 is actuated, and as a result the 2nd shift register channel can be actuated.
JP56055001A 1981-04-14 1981-04-14 Logic system Pending JPS57169846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56055001A JPS57169846A (en) 1981-04-14 1981-04-14 Logic system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56055001A JPS57169846A (en) 1981-04-14 1981-04-14 Logic system

Publications (1)

Publication Number Publication Date
JPS57169846A true JPS57169846A (en) 1982-10-19

Family

ID=12986410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56055001A Pending JPS57169846A (en) 1981-04-14 1981-04-14 Logic system

Country Status (1)

Country Link
JP (1) JPS57169846A (en)

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