JPS57164492A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57164492A
JPS57164492A JP56049760A JP4976081A JPS57164492A JP S57164492 A JPS57164492 A JP S57164492A JP 56049760 A JP56049760 A JP 56049760A JP 4976081 A JP4976081 A JP 4976081A JP S57164492 A JPS57164492 A JP S57164492A
Authority
JP
Japan
Prior art keywords
level
signal
phi21
word line
activated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56049760A
Other languages
Japanese (ja)
Other versions
JPS6238798B2 (en
Inventor
Shoji Ishimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56049760A priority Critical patent/JPS57164492A/en
Publication of JPS57164492A publication Critical patent/JPS57164492A/en
Publication of JPS6238798B2 publication Critical patent/JPS6238798B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To increae the quantity of signal of a memory cell and to enlarge the margin of operation of a sense amplifier, by bringing up the level of a selection word line to a level which is higher than the power supply voltage after the sense amplifier is activated. CONSTITUTION:When a control signal phi21 is activated, a selection word line 21 becomes a level ''1'' and its electric potential becomes the supply voltage level which is the level ''1'' of the signal phi21. When the word line 21 is activated, information from the cell capacity and dummy cell capacity appears in bit lines 24 and 26. An activated signal phi22 to an input terminal 42 of a sense amplifier consisting of MOSFETs Q26 and Q27 is generated behind the signal phi21. By activation of the signal phi22, minute difference signals of the bit lines 24 and 26 become perfect level ''1'' or level ''0''. Moreover, the levels of the signal phi21 and the word line 21 can be brought up to a level of the signal phi21 and the word line 21 can be brought up to a level which is higher than the supply voltage with a delay time behind the signal phi22. Therefore, the level ''1'' of the cell capacity can be refreshed to the same level as the bit line 24. As a result, the quantity of the signal of cell is increased and the margin of the sense amplifier is enlarged.
JP56049760A 1981-04-02 1981-04-02 Semiconductor device Granted JPS57164492A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56049760A JPS57164492A (en) 1981-04-02 1981-04-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56049760A JPS57164492A (en) 1981-04-02 1981-04-02 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS57164492A true JPS57164492A (en) 1982-10-09
JPS6238798B2 JPS6238798B2 (en) 1987-08-19

Family

ID=12840133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56049760A Granted JPS57164492A (en) 1981-04-02 1981-04-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57164492A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57133589A (en) * 1981-02-12 1982-08-18 Fujitsu Ltd Semiconductor circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57133589A (en) * 1981-02-12 1982-08-18 Fujitsu Ltd Semiconductor circuit

Also Published As

Publication number Publication date
JPS6238798B2 (en) 1987-08-19

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