JPS57162161A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS57162161A
JPS57162161A JP56044697A JP4469781A JPS57162161A JP S57162161 A JPS57162161 A JP S57162161A JP 56044697 A JP56044697 A JP 56044697A JP 4469781 A JP4469781 A JP 4469781A JP S57162161 A JPS57162161 A JP S57162161A
Authority
JP
Japan
Prior art keywords
address
row
signal
buffer
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56044697A
Other languages
Japanese (ja)
Inventor
Yoshihiro Takemae
Tomio Nakano
Takeshi Ohira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56044697A priority Critical patent/JPS57162161A/en
Publication of JPS57162161A publication Critical patent/JPS57162161A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To quicken the operating speed and to reduce the power consumption, by giving a row address signal from a row address buffer at an address switch at a desired single row decoder only. CONSTITUTION:Address switches A0-A7 are provided for each of row address buffers CB0-CB7 and between row decoders 10 and 20. The address switch A0 receives a row address signal from the row address buffer CB0. According to an output signal AR7 of a column address buffer RB7, a column address signal AC10 is given to a lower stage row decoder 10 or a row address signal AC20 is given to an upper row decoder 20. This is similarly done for other address switches A1-A7.
JP56044697A 1981-03-28 1981-03-28 Semiconductor storage device Pending JPS57162161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56044697A JPS57162161A (en) 1981-03-28 1981-03-28 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56044697A JPS57162161A (en) 1981-03-28 1981-03-28 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS57162161A true JPS57162161A (en) 1982-10-05

Family

ID=12698602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56044697A Pending JPS57162161A (en) 1981-03-28 1981-03-28 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS57162161A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS528739A (en) * 1975-07-10 1977-01-22 Fujitsu Ltd Electronic circuit
JPS55135392A (en) * 1979-04-04 1980-10-22 Nec Corp Memory circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS528739A (en) * 1975-07-10 1977-01-22 Fujitsu Ltd Electronic circuit
JPS55135392A (en) * 1979-04-04 1980-10-22 Nec Corp Memory circuit

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