JPS5715534A - Field programmable logical array - Google Patents

Field programmable logical array

Info

Publication number
JPS5715534A
JPS5715534A JP9089880A JP9089880A JPS5715534A JP S5715534 A JPS5715534 A JP S5715534A JP 9089880 A JP9089880 A JP 9089880A JP 9089880 A JP9089880 A JP 9089880A JP S5715534 A JPS5715534 A JP S5715534A
Authority
JP
Japan
Prior art keywords
array
delay time
storage cell
output
fixed storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9089880A
Other languages
Japanese (ja)
Inventor
Hiroaki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9089880A priority Critical patent/JPS5715534A/en
Publication of JPS5715534A publication Critical patent/JPS5715534A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To inspect and guarantee the worst propagation delay time at a manufacture side in unprogrammed state, by incorporating a fixed storage cell array and an additinal input and output circuit to an IC chip so that the measurement of the worst propagation delay time is possible. CONSTITUTION:A field programmable logical array (FPLA) consisting of an AND array 1, an OR array 2, plus an input circuit 3, an OR driver 4 and an OR output 5, and obtaining an arbitrary output of logical product and sum format relating to I1-In at Z1-Z is provided with fixed storage cell arrays 7, 8, 11 programming a pattern in advance to be the worst case in the signal delay time in actually realizing when the arrays 1, 2 are programmed in an arbitrary pattern, and unprogrammed fixed storage cell arrays 9, 10. Further, the fixed storage cell array selection input Ed of an additional input circuit 6 is kept at high level, a pulse is inputted to an input Id and an output Zd is obtained at an additional output circuit 12 to measure the worst propagation delay time.
JP9089880A 1980-07-03 1980-07-03 Field programmable logical array Pending JPS5715534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9089880A JPS5715534A (en) 1980-07-03 1980-07-03 Field programmable logical array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9089880A JPS5715534A (en) 1980-07-03 1980-07-03 Field programmable logical array

Publications (1)

Publication Number Publication Date
JPS5715534A true JPS5715534A (en) 1982-01-26

Family

ID=14011215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9089880A Pending JPS5715534A (en) 1980-07-03 1980-07-03 Field programmable logical array

Country Status (1)

Country Link
JP (1) JPS5715534A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0489571A2 (en) * 1990-12-04 1992-06-10 Xilinx, Inc. Estimating resistance and delay in an integrated circuit structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0489571A2 (en) * 1990-12-04 1992-06-10 Xilinx, Inc. Estimating resistance and delay in an integrated circuit structure
EP0489571A3 (en) * 1990-12-04 1993-06-16 Xilinx, Inc. Estimating resistance and delay in an integrated circuit structure

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