JPS57152752A - Packet editing system - Google Patents
Packet editing systemInfo
- Publication number
- JPS57152752A JPS57152752A JP56037816A JP3781681A JPS57152752A JP S57152752 A JPS57152752 A JP S57152752A JP 56037816 A JP56037816 A JP 56037816A JP 3781681 A JP3781681 A JP 3781681A JP S57152752 A JPS57152752 A JP S57152752A
- Authority
- JP
- Japan
- Prior art keywords
- packet
- dmactl
- controller
- call control
- control memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
PURPOSE:To reduce the quantity of software for packet processings, by rewriting originating side information in the packet header of a packet to terminating side information in accordance with contents of a call control memory when the received packet is transferred to a storage device. CONSTITUTION:When a packet comes to a subscriber's interface part, a start signal ST is inputted to a controller DMACTL, and the controller DMACTL issues the use request for a data bus DB, and the packet is transferred to an RAM when this request is permitted. Since a route number RN, a logical channel group LCGN, and a logical channel number LCN refer to a call control memory LIM, the first and the second bytes of the packet header are set to registers R0 and R1. At this time, an address selector ADSEL selects registers R0 and R1, and the 0th, the first, and the second bytes of the packet are read out from the call control memory LIM, and the controller DMACTL writes them in order from the start address of storage in the RAM.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56037816A JPS57152752A (en) | 1981-03-18 | 1981-03-18 | Packet editing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56037816A JPS57152752A (en) | 1981-03-18 | 1981-03-18 | Packet editing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57152752A true JPS57152752A (en) | 1982-09-21 |
Family
ID=12508042
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56037816A Pending JPS57152752A (en) | 1981-03-18 | 1981-03-18 | Packet editing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57152752A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60246152A (en) * | 1984-05-22 | 1985-12-05 | Nec Corp | Data exchange processing system |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51138103A (en) * | 1975-05-09 | 1976-11-29 | Western Electric Co | Packet exchanger |
-
1981
- 1981-03-18 JP JP56037816A patent/JPS57152752A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51138103A (en) * | 1975-05-09 | 1976-11-29 | Western Electric Co | Packet exchanger |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60246152A (en) * | 1984-05-22 | 1985-12-05 | Nec Corp | Data exchange processing system |
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