JPS60246152A - Data exchange processing system - Google Patents

Abstract

PURPOSE:To improve the processing ability of a central processing unit by allowing a hardware means to analyze immediately control information when the control information included in reception data is stored in a temporary storage circuit and storing event information in a main storage device prior to the storage of content of the received data in place of the control information. CONSTITUTION:A reception circuit 1 transmits data to a buffer memory 2 in the unit of byte at first when a pattern not being a flag sequence in the input is stored in a data storage device. The buffer memory 2 stores the data transmitted sequentially and when the data reaches a designated m bits in advance, a control circuit 6 allows a comparator circuit 4 to read the said m bits immediately and reads sequentially plural pieces of information in the unit of m bits in the storage memory 3 and gives the result to the comparator circuit 4. The comparator circuit 4 compares both inputs of m bits and when they are coincident, the circuit 4 gives the coincidence information to the control circuit 6. Then the control circuit 6 transfers the event information to a prescribed location of a main storage device 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (Differential Fields of Application) The present invention relates to a BAF'i data exchange processing method, a data exchange processing method that performs block transmission processing including control information following a special length transmission start flag.

(Prior Art) Conventionally, in data exchanges that handle data in blocks, such as message exchanges and packet exchanges, multiple blocks of received data are stored in storage circuits each having a fixed length, for example, 4 bytes. For example, each time these storage circuits are filled with data,
Transfer and store it in the specified location on the storage device. Therefore, when the received data of each central processing unit fliVi reached a predetermined amount in the main memory, the multiple bits that constitute the first control information of the received stored data were extracted and input analysis processing was performed to determine the amount. The event information is stored in place of the read control information in preparation for the next process.

(Problem to be Solved by the Invention) In order to avoid data loss during transmission and reception, this processing method preferentially executes data transfer processing between the storage circuit for a certain number of bales of bits and the data storage device. Since the control information is processed in between, there is a drawback that if the processing is interrupted, the troublesome process of saving it to the storage device and the corresponding time are lost.

(Means for Solving the Problems) In order to solve the above problems, the present invention analyzes the control information by hardware means immediately after the control information included in the received data is stored in the temporary storage circuit. , is a data exchange processing method that can shorten program processing time by storing event information instead of this control information in an IC in the main storage device prior to storing received data self-answers, and is a data exchange method that performs block transmission. In the processing mechanism, a storage means for storing information consisting of a plurality of m bits, an accumulation means for temporarily accumulating received data in units of n (05m) bits, and a storage means following the received flag sequence (start flag). a comparison means for detecting a match between the m-bit information temporarily stored in the storage means and the m-bit information of the storage means; and when a match is obtained by the comparison means, event information corresponding to this information is stored in the main memory. and a writing means for storing data in a predetermined location ii.

(Embodiment) FIG. 1 is a schematic diagram showing an embodiment of the present invention, and shows only the functions necessary for explaining the present invention among the data exchange processing system. In the figure, a damaged circuit (Rh, C) 1 connected to a communication line and a buffer memo that temporarily stores its output in units of n bits! j(BM)2, information consisting of, for example, 128 types of m bits, and event information related to processing in the central processing unit corresponding to this information are stored in pairs! j (HM) 3, a comparison circuit (COMF) 4 that detects a match between the first m bits stored in the buffer memory 2 and the 30m bits of the holding memory; an event sending circuit (gs) that reads event information from the written location in the memory 3 and sends this event information to the main memory (MM) 8;
5, and a control circuit (CONT) that controls each of the above functional circuits.
) 6, the reception control system consists of the central processing unit it
, (CPU) 7 bus. Note that the main storage device 8 is also connected to this bus. Further, although not shown, a plurality of the reception control systems and a plurality of transmission control systems are also connected to the bus.

Next, the operation of this embodiment will be explained. For example, if the flag sequence is composed of one byte, the receiving 4M circuit 1 has a data storage circuit with a length of at least one byte, and the data is continuously transmitted. The incoming 7-lag sequence is read into this data storage circuit to synchronize the flag sequence.

Therefore, the receiving circuit 1 does not send this information to the buffer memory 2 while the input is a flag sequence, and only when a pattern (data) that is not a flag sequence is accumulated in the data storage circuit VC, this data is sent in 1-byte units to the buffer memory 2. Send to memory 2. At this time, the receiving circuit 1 notifies the simultaneous pressure control circuit 6 that the first data has been received. Next, the buffer memory 2 accumulates the data sent sequentially,
When the data reaches a predetermined m bits (for example, 2 bytes), the control circuit 6 is informed that m bits have been stored. The control circuit 6 immediately transfers these m bits to the comparator circuit 4, and sequentially outputs a plurality of pieces of information in units of m bits from the holding memory 3 and supplies them to the comparator circuit 4. The comparator circuit 4 compares the inputs of the dual-use bits, and when it sees -, it notifies the control circuit 6 of a match, stops the output of the next information from the holding memory 3, and also sends an event (log). ) Tell them that the road also matches. Therefore, the event sending circuit 5 reads the event information stored in the holding memory 3 corresponding to the m-bit information of the matched data. Next, the control circuit 6 transfers this event information to a predetermined location in the main memory device 8 designated in advance by the central processing unit 7. The above operations from storing m bits to transferring the event information r to the main memory 8 are performed vertically by hardware, so the data reception speed is, for example, 48
If it is kilobits/second, it can be finished without waiting for the arrival of 1 byte following m bits. Furthermore, even if the data reception speed becomes faster, the capacity of the buffer memory (ftn)
The received data accumulated in the buffer memory 2 since 0, which can be easily processed by setting it to m, is n bits, so that the buffer memory lJ2 is full.

)K, the control circuit 6 stores the remaining n−m bits excluding the first m bits in the main memory 8 specified in advance.
Transfer to the designated location &. Thereafter, the control circuit 6, in the same way as the conventional method, stores the data in the main storage device 8 every time the backup memory 2 becomes full, by filling in the previously transferred data until the end of the data block. Continue forwarding.

In the above embodiment, m-bit information and event information corresponding to this information are stored in pairs in the holding memory 2, and this event information is read in the event sending circuit 5. Without storing the event information, the control unit ai6 sequentially specifies addresses to extract m-bit information from the holding memory, and the address when a match is found in the comparison circuit 4 is transmitted to the event sending circuit. It is also possible to have the sending circuit read event information from a correspondence table between addresses and event information.

Furthermore, since the correspondence between the control information of the first m bits of data and the event information is determined when the processing program is created or updated, processing 7 to the main memory is
'Following the storage of the program, the central processing unit can store the program in the holding memory or event sending circuit via the bus.0 (Effects of the Invention) As described in detail above, according to the present invention, all reception When the reception of the block data is completed, the event information for this block data has been obtained, so the central processing unit can immediately perform the tamak processing determined by the event, and the central processing unit This has the effect of increasing processing capacity and providing a processing method effective for high-speed data transmission.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. 1... Receiving circuit (EC), 2... Buffer memory (BM), 3... Holding memory (H
M), 4... Comparison circuit (COMF), 5...
...Event sending circuit (ES), 6...Control circuit (CON'J">, 7...Central processing unit (
CPU), 8...amphibian storage CMM). Agent: Patent attorney Fu Uchihara / Figure 1

Claims (1)

[Claims] In a data exchange processing method that performs block transmission, a storage means for storing information consisting of a plurality of m bits, an accumulation means for temporarily storing received data in units of n (n5m) bits, and a received flag sequence (-start flag) Next, comparing means detects a match between the m-bit information temporarily stored in the storage means and the m-bit information of the storage means, and event information corresponding to this information when a match is obtained by the comparing means. a data exchange processing method, comprising: a data exchange means for storing the data at a predetermined location in a main storage device.