JPH0267848A - Transfer system for variable length data frame - Google Patents

Abstract

PURPOSE:To improve the reliability against the occurrence of data error on a transmission line by dividing data on the transmission line by fixed length slots starting with identifiers and properly using identifiers to transfer a variable length data frame whose length is integer times as long as that of the fixed length slot. CONSTITUTION:Data to be transferred is divided to plural fixed length slots 11. The first fixed length slot 11 is provided with an identifier 12 indicating the first slot and is provided with an address part 13 indicating the transmission destination following the identifier, and a data part 14 is aranged in the other part of the fixed length slot 11. The next fixed length slot 11 is provided with an intermediate identifier 15 at the head, and data following data in the data part 14 of the first fixed length slot 11 is arranged in the data part 14 following the identifier 15. An arbitrary number of fixed length slots 11 belonging to the same data frame are continuous hereafter, and the whole of data to be transferred is transferred by fixed length slots 11. Thus, an influence upon the reception side is reduced though data error occurs on the transmission line, and a high reliability is obtained.

Description

[Detailed Description of the Invention] [Summary] Regarding a variable length data frame transfer method in a communication system that communicates messages, high reliability can be achieved by reducing the influence on the receiving side due to errors in bit patterns that identify data frames. The purpose is to provide a variable length data frame transfer method that uses data frames on a transmission path to communicate messages between a communication control device connected to multiple terminal devices and a transmission path. In the data frame transfer method, a variable length data frame whose length is an integral multiple of a fixed length slot is transferred on the transmission path, and the slot is placed at the beginning of each fixed length slot in the data frame. The configuration is such that an identifier is provided to indicate whether it is a fixed-length slot in the middle of the same data frame or a fixed-length slot in the middle of the same data frame, and further, synchronization protection in the receiving section is performed using the identifier provided in each fixed-length slot of the data frame.

At the same time, high reliability (reducing data errors on the transmission path or reducing the effects of errors) is required.

[Field of Industrial Application] The present invention relates to a variable length data frame transfer method in a communication system for message communication.

In recent years, LA has been used as a communication system for message communication.
N (Local Area Network), high-speed packet network, I5DN (Integrated Service Digital Communication Network), etc. have been put into practical use and are now in use. In such communication systems, the speed and capacity are increasing, and along with this, there is a trend toward wider area and larger scale.

In the above communication system, the communication control devices (equipped with the function of storing and exchanging messages) installed in each node are connected by a transmission path. Transfer efficiency in transferring data frames on the road [Prior art] An explanatory diagram of a conventional example is shown in FIG.

Each of the plurality of communication control devices 60 to 63 is a terminal device 60.
1,611...631 (only one of each is shown in the figure) are connected, and multiple transmission lines are connected, and messages from each terminal are stored and exchanged via the transmission lines under the control of the communication control device. will be held. Although this diagram only shows a transmission path in one direction, in reality, a transmission path in the opposite direction is also provided.

Each communication control device is connected by a transmission path 610...630, and the structure of the variable length data frame on the transmission path is the sixth
The transmission path 620 in the figure is shown. This frame structure follows a transmission control procedure known in the art as HDLC (High Level Data Link Control Procedure), in which a unique flag pattern (indicated by F) is provided at the beginning, followed by an address field, and then a data field. (including a frame check sequence for error checking), the last flag also represents the flag at the beginning of the next frame, data of arbitrary length can be transmitted by the data part in this frame structure. can.

The flag pattern is “01111110” as shown in the figure.
In areas other than flag patterns, when the sending side sends data with five or more consecutive "1"s, it inserts "0" after transmitting a pattern of five consecutive "l"s, and On the side, pattern unity is achieved by deleting "°°O" after receiving a pattern of 5 consecutive "1"s.The address part of the frame indicates the destination of the data in the frame. The communication control device on the side refers to this address and retransmits this data frame to a predetermined transmission path or terminal.

[Problems to be Solved by the Invention] According to the conventional method shown in FIG. 6, an error occurs in data frame identification due to the occurrence of a data error of l focus for the flag pattern on the transmission path.

In other words, if the flag pattern cannot be detected, the boundaries within the data frame (flags, addresses, data, etc.) will be incorrectly identified, resulting in incorrectly recognized parts of the address that are not intended to be addresses. Received by a destination that is unrelated to the destination and has a significant impact. In the past, errors in the address field could be dealt with by adding an error correction code, but there was no defense against data errors related to flag patterns for identifying variable-length data frame boundaries.

Conversely, if an l-focus data error occurs in an area other than the flag pattern, a false flag pattern is generated and the data frame is divided, and a message is sent to an incorrect destination due to processing for a false address.

As described above, the conventional system has a problem in that reliability is low when data errors occur on the transmission path.

SUMMARY OF THE INVENTION An object of the present invention is to provide a variable length data frame transfer system that can reduce the influence on the receiving side even if an error occurs in a bit pattern that identifies a data frame, and can achieve high reliability.

[Means for Solving the Problems] A basic configuration diagram of a variable length data frame according to the present invention is shown in FIG.

In the figure, 10 is one variable length data frame, 11 is a fixed length slot, 12 is a start identifier indicating that it is the first fixed length slot of the data frame, 13 is an address section, 14 is a data section, and 15 is a data frame. This is an intermediate identifier indicating that the slot is a fixed length slot 7) that follows the preceding fixed length slot.

The present invention makes the length of the data frame on the transmission path an integral multiple of the fixed length slot, so that the data to be transferred is transferred using a data frame consisting of a plurality of consecutive fixed length slots, and the data frame on the receiving side is This facilitates synchronization and provides an identifier at the beginning of each fixed length slot to identify the data of the l data frame on the receiving side.

[Operation] Data to be transferred is divided into a plurality of fixed length slots. At this time, the first fixed length slot 11 is provided with an identifier 12 representing the beginning, followed by an address field 13 representing the transmission destination.
is provided, followed by placing data in the remaining portion of the fixed length slot.

The next fixed-length slot following this is provided with an intermediate identifier 15 at the beginning indicating that it is a slot that follows the previous fixed-length slot, and the subsequent data section 14 contains data following the data section of the first fixed-length slot. is placed. below,
An arbitrary number of fixed length slots belonging to the same data frame are consecutively transferred, and all data to be transferred is transferred using the fixed length slots. If a fraction occurs in the data due to the fixed length slot, it is made into a fixed length by adding dummy bits or the like.

When the transfer of one data frame is completed, the transfer of another data frame is subsequently performed, and the fixed length slot 7) at the head thereof is provided with a head identifier.

[Example] Fig. 2 is a data frame configuration diagram of Embodiment 1, Fig. 3 is a data frame configuration diagram of Embodiment 2, Fig. 4 is a configuration diagram of a communication control device implementing the present invention, and Fig. 5 ( a) is a block diagram of the transmitting section, and FIG. 5 [present] is a block diagram of the receiving section.

First, the frame structure of the first embodiment shown in FIG. 2 will be explained.

In FIG. 2, 20 is an l data frame, 21 is a fixed length slot, 22 FS is a flag pattern indicating the start of a data frame (and the start of a fixed length slot), 23
24 is an address part, 24 is a data part, and FC 25 is a flag pattern representing the middle of the data frame (fixed length slot in the middle).

In the case of the first embodiment, one data frame 20 includes a flag pattern FS, 22, an address field 23, and a data field 24 to form a fixed length slot at the beginning, and the following fixed length slot has a flag pattern FC, 25 and data. 24, followed by similar fixed length slots, and a plurality of slots constitute one data frame.

The flag patterns FS and FC are each composed of different bit patterns, and by increasing the Hamming distance between both bit patterns, errors can be corrected.For example, as FC, "00110011"
''', use "11001100" as FS.

The data frame of this first embodiment is synchronized protected on the receiving side with the I position of each flag pattern FS and FC.

That is, it is possible to draw in the flag pattern as a synchronization signal and achieve synchronization using forward protection and backward protection, which are known techniques.

Therefore, by using this flag pattern, synchronization is maintained even if a bit error occurs in the flag pattern, so the possibility of erroneous identification of slot positions (data frame boundary positions) is greatly reduced.

Next, the frame structure of the second embodiment shown in FIG. 3 will be explained.

In FIG. 3, 30 is one data frame, 31 is a fixed length slot, 32 is a slot multiplex frame flag pattern F,
Does 33 represent the beginning of a fixed slot? 3m focus C13
4 is an address part, 35 is a data part, and 36 is a control bit (control bit C) indicating that it is a fixed length Scott.
negation logic).

In the case of this second embodiment, one data frame 30 includes a control bit C, 33, an address field 34, and a data field 35 to form a leading fixed-length SCOTT, and the following fixed-length SCOTT includes a control bit C936 and a data field. 35, followed by similar fixed length slots, and a plurality of slots constitute one data frame.

The slot multiplex frame flag pattern F32 is "'01111110°" as before or the above FS, FC
You can use the pattern given in the example.

In this second embodiment, synchronization protection is applied to a frame in which a plurality of slots are multiplexed by detecting the slot multiplex frame flag pattern F, 32 on the receiving side.

Next, the configuration of a communication control device in which the present invention is implemented will be explained with reference to FIG.

In the figure, 40 is a communication control device, 41 is a plurality of transmitting sections, 42 is a switch section, 43 is a terminal corresponding section, 44 is a plurality of receiving sections,
Reference numeral 45 represents a transmission line on the transmitting side, 46 represents a transmission line on the receiving side, and 47 represents a transmission/reception line to the terminal.

The communication control device 40 receives data signals from a plurality of transmission paths 46 on the receiving side in a receiving section 44, receives a transmission signal from a terminal in a terminal corresponding section 43, and sends both signals to the conventional switch section 42. The data is either sent from the transmitter 41 to the transmission path through the same exchange process (accumulation and processing in the memory, selecting the destination route and sending it out), or it is sent to the terminal via the terminal support unit 43. Sent out. The variable length data frame transfer method of the present invention is based on each transmission path 4 connecting the transmitting section 41 and the receiving section (not shown) of the other party's communication control device in FIG.
5 and each transmission path 46 connecting the receiving unit 44 with another communication control device (not shown).

FIG. 5(a) shows a block diagram of the transmitter, and FIG. 5(b) shows a block diagram of the receiver.

To explain the transmitter in FIG. 5(a), reference numeral 50 is a transmitter, 51 is a transmitter, 52 is a transmitter selector, 53 is a control pattern insertion circuit, 54 is a control circuit, and 55 is a slot counter (Embodiment 1). 56 represents a buffer.

To explain the operation, a control signal for starting variable length data frame transfer from the switch section 42 in FIG.
, the control circuit 54 takes the data frame into the buffer 56.

Slot counter/Scott multiplex frame counter (
A slot counter 55 (hereinafter simply referred to as a "slot counter") notifies the control circuit 54 of the timing for transmitting the beginning of each fixed-length slot to the transmission path in the case of the first embodiment (FIG. 2), and in the case of the second embodiment (FIG. 2). (Figure 3) Furthermore, the control circuit 54 is notified of the transmission timing of the slot multiplex frame flag pattern F32.

In accordance with the timing notified by the slot counter 55, the control circuit 54 simultaneously identifies whether or not the data block in the buffer 56 to which the next slot is to be transferred is at the starting position of a series of data frames, and performs the processing as shown in FIG. The control pattern insertion circuit 53 is driven according to the format shown in FIG. The transmission selector 52 is switched to the transmission circuit 5 side only at the timing of control pattern transmission, and transmission is performed on the transmission path in the format shown in FIG. 2 or 3.

The control pattern insertion circuit 53 selects the flag pattern FS or FC, C=1 or C-0 depending on whether or not the continuous slot 7) data is at the head position of the data frame.

In this case, for flag patterns FS and FC, FS
=11001100. It is assumed that several bit errors can be corrected by setting FC=00110011 or by code conversion such as 8BIOB (a known transmission line encoding format that adds redundant bits).

Furthermore, for the control bit C, an error correction code is added on the transmission path, for example, C=1 is "zi", c=o
can be made into a 3-bit redundant configuration of "000" so that a 1-bit error can be corrected by majority logic.

Next, the configuration of the receiving section shown in FIG. 5(b) will be explained. Figure 70
71 is a control circuit, 72 is a buffer, 73 is a control pattern deletion circuit, 74 is a synchronization protection circuit, 75 is a control pattern detection circuit, and 76 is a reception circuit.

The data frame received from the transmission path is received by the reception circuit 76, and the control pattern detection circuit 75 receives the data frame from the synchronization protection circuit 7.
According to the slot timing notified by 4, the flag pattern FS/FC is detected in the case of the first embodiment, and the flag pattern FS/FC is detected in the case of the second embodiment.
In this case, control bit C is detected.

Further, if a bit error occurs in the control pattern, the control pattern detection circuit 75 performs error correction and notifies the control circuit 71 of the result.

This notification also includes information as to whether or not it is the beginning position of the data frame.

Each slot is assigned a flag pattern FS, FC (in the case of the first embodiment) or F, by the control pattern deletion circuit 73.
Deletion of pattern C (in the case of Embodiment 2) (control circuit 71
(the timing is notified by), the control circuit 7
1 is received into the buffer 72 according to the instruction. Since the position occupied by each slot in the data frame is identified by the control circuit 71, the variable length data frame is reconfigured in the buffer 72 (reconfigured from the frame configuration on the transmission path to the data processed by the original switch unit). ) and then transferred to the switch section.

[Effects of the Invention] According to the present invention, by dividing a transmission path into fixed-length slots starting with an identifier and using the identifiers appropriately, it is possible to transfer variable-length data frames in the sense of an integral multiple of the fixed-length slot. can. Further, even when an error occurs in the identifier, synchronization protection can eliminate identification errors of data frame boundary positions and slot positions, and the reliability of boundary identification can be significantly improved.

Furthermore, by using a flag pattern with a large Hamming distance or one with redundant bits added as an identifier, it is possible to prevent identification errors at border positions.

Block diagram, Fig. 5(a) is a block diagram of the transmitter, Fig. 5(b)
6 is a block diagram of a receiving section, and FIG. 6 is an explanatory diagram of a conventional example.

In Figure 1, lO: 1 data frame of variable length ll: fixed length slot 12: Start identifier 13 Near address part 14: Data section 15: Intermediate identifier Patent applicant: Fujitsu Limited Sub-agent Patent Attorney Hosaka Airi

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of a variable length data frame of the present invention, FIG. 2 is a frame configuration diagram of Embodiment 1 of the present invention, FIG. 3 is a frame configuration diagram of Embodiment 2 of the present invention, and FIG. 4 is a difficult problem for a communication control device implementing the present invention.

Claims (2)

[Claims] (1) In a variable length data frame transfer method that uses data frames on the transmission path to communicate messages between a communication control device connected to multiple terminal devices and a transmission path, the transmission path has a fixed length. A variable-length data frame whose length is an integral multiple of the slot is transferred, and the start position of each fixed-length slot in the data frame indicates whether the slot is the first slot of the data frame or a fixed-length slot in the middle of the same data frame. 1. A variable-length data frame transfer method, characterized in that an identifier is provided to display a variable-length data frame. (2) The variable length data frame transfer method according to claim 1, wherein synchronization protection is performed in the receiving section using an identifier provided in each fixed length slot of the data frame.