JPS61100049A - Packet exchange line control system - Google Patents

Abstract

PURPOSE:To attain effective use of a data part by separating a buffer area storing a reception packet into a header part and the data part of the packet. CONSTITUTION:In designating a reception command by the type of command, a packet header buffer is concentrated on a specific area of a main memory 12 and an area continuous to a packet header processing program is assigned. The inside of the main memory 12 is provided with an idle buffer list table consecutive to a channel command area and idle packet data buffers are regis tered in the table. a link level control part 2 reads the channel command, accesses the idle buffer list table to reserve one of idle buffers. When the data of the reception buffer is long, an additional idle buffer is reserved at a required point of time.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a communication control method for realizing data transmission control between a network and a terminal in a packet switching system.

(Conventional Technology) Conventionally, a line control section in this type of packet switching equipment has been comprised of a processor section that performs packet-level processing and a link-level control section that performs link-level processing. In addition to link level protocol processing, the link level control section included a channel function for transferring transmitted and received data to the processor section, and a line control function for transmitting and receiving data to and from the line.

FIG. 1 shows a packet switching line according to the prior art.

FIG. 2 is a block diagram showing a device configuration for realizing an example of a control method. In FIG. 1, the processor section 1 is composed of a processor unit 11 and a main memory 12.
The link level control section 2 includes a memory access control section 21 , a microcontroller 22 , and a line control section 23 . The link level control section 2' has the same configuration as the link level control section 2.

The division from the processor section l to the link level control section 2 is realized by setting a channel command in the main memory 12, and having the link level control section 2 record the channel command from the main memory 12 and execute it. Transfer of transmitted/received data between the link level 1 NIJ#J section 2 and the processor section 1 is performed by accessing the main memory 12 from the link level control section 2 in accordance with a channel command.

Since the above is already a well-known technique, the details will be omitted.

In order for the link level control unit 2 to realize the above functions, it is necessary to read and interpret channel commands, calculate sending and receiving addresses, and monitor command completion. These are realized by the software of the microcontroller 22.

Memory access 1 controller 21 is microcontroller 2
According to the memory access instructions from 2, main memo IJ
This is a circuit for writing/reading to/from 12.

FIG. 4 is an explanatory diagram showing a format in which a receive packet buffer address and the packet buffer length can be specified within a channel command.

(Problems to be Solved by the Invention) In FIG. 4, when only the packet header section is present, the length of the received packet is very short, and when it includes the packet data section, it becomes long. In such a method, until a packet is received, it is not possible to judge whether the packet length is long or a certain b is short, so the bucket buffer length must be specified as long, and short packets are stored in a buffer with a long b buffer length. It has the disadvantage that only the header can be entered, creating a wasteful empty area.

Further, in the above case, when an 8-bit, or 16-bit, microprocessor is used as the processor unit 11 of the processor section 1, the main memory area that can be directly accessed by instructions is limited. Therefore,
Processor unit 1 due to constraints on the memory size that can be implemented
However, this method has disadvantages in that it causes a decrease in the processing performance of the main memory 12 and an insufficient capacity of the main memory 12.

The object of the present invention is to eliminate the above-mentioned drawbacks by separating the buffer area for storing received packets into the header section and the data section of the packet, and to provide a packet switching line configured to enable effective use of the data section. The objective is to provide a control method.

(Means for Solving the Problems) The packet switching line control system according to the present invention includes a processor unit and a main memory for performing packet level processing, a memory access unit, a microcontroller, and a circuit control system. This is an improved method for realizing communication control of a line interface of a packet switch, and includes one or more link level control units for performing link level processing.

In the present invention, the main memory is configured to include at least a channel command area and an empty buffer list table area in the above configuration.

The channel command area is for setting channel commands.

The empty buffer list table area is for reference when securing one empty buffer by the link level control unit and using it for received packet data.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an explanatory diagram showing an example of the format of a channel command for realizing the packet-switched line control system according to the present invention.

FIG. 2 is an explanatory diagram showing an example of area allocation of the main memory 12 performed according to the present invention.

In FIG. 1, when a receive command is designated as the command type, only the top address of the ladder buffer is designated to the packet inside this channel command. The buffer length of the ladder buffer for packets is fixed, and there is no need to specify the buffer length inside the channel command.

As shown in FIG. 2, the packet ladder buffer is concentrated in a specific area of the main memory 12, and an area continuous with the packet header processing program is allocated. Inside the main memory 12, there is an empty buffer list table that is continuous to the channel command area, and empty packet data buffers are placed here.

After reading the channel command, the link level control unit 2 accesses the empty buffer list table and reserves one empty buffer.

When the received packet data is of length A, an additional empty buffer is reserved at the necessary time.

(Effects of the Invention) As explained above, the present invention has the first effect that the ladder buffer area for the packet can be secured by working with the packet header processing program, and that the processing speed can be increased by improving the processing speed. , Second, the required number of bucket data buffers are allocated from the common pool according to the length of the received packet.
Since it can be secured at that point, the usage rate of the bucket data buffer can be improved, and the required main memory capacity can be reduced.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing an example of the format of a channel command realized by the present invention. FIG. 2 is an explanatory diagram showing an example of main memory area allocation realized according to the present invention. FIG. 3 is a block diagram showing an example of a device configuration for realizing a conventionally employed packet switching line control system. FIG. 4 is an explanatory diagram showing an example of the format of a channel command realized by the prior art. 1... Processor unit 2.2'... Link level control unit 11... Processor unit 12... Main memory 21... Memory access control line 22... Microcontroller 23... Line control unit Patent Applicant NEC Corporation Agent Patent Attorney Hisashi Inoro Figure 1 Figure 22

Claims (1)

[Claims] One or more link-level controllers that include a processor unit and a main memory to perform packet-level processing, a memory access control unit, a microcontroller, and a line control unit to perform link-level processing In the packet switching line control method for realizing communication control of a line interface of a packet switch, the main memory includes at least a channel command area for setting channel commands, and a channel command area for setting channel commands; and an empty buffer list table area for reference when securing empty buffers and using them for received packet data.