JPS57143970A - Self-testing system for multifrequency signal receiver - Google Patents

Self-testing system for multifrequency signal receiver

Info

Publication number
JPS57143970A
JPS57143970A JP56029714A JP2971481A JPS57143970A JP S57143970 A JPS57143970 A JP S57143970A JP 56029714 A JP56029714 A JP 56029714A JP 2971481 A JP2971481 A JP 2971481A JP S57143970 A JPS57143970 A JP S57143970A
Authority
JP
Japan
Prior art keywords
circuit
output
fault
circuits
discrete fourier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56029714A
Other languages
Japanese (ja)
Other versions
JPH0343819B2 (en
Inventor
Akira Fukui
Shiro Kikuchi
Masaki Ehata
Makoto Mori
Takaaki Osaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP56029714A priority Critical patent/JPS57143970A/en
Publication of JPS57143970A publication Critical patent/JPS57143970A/en
Publication of JPH0343819B2 publication Critical patent/JPH0343819B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q1/00Details of selecting apparatus or arrangements
    • H04Q1/18Electrical details
    • H04Q1/30Signalling arrangements; Manipulation of signalling currents
    • H04Q1/44Signalling arrangements; Manipulation of signalling currents using alternate current
    • H04Q1/444Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies
    • H04Q1/45Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling
    • H04Q1/457Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling with conversion of multifrequency signals into digital signals
    • H04Q1/4575Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling with conversion of multifrequency signals into digital signals which are transmitted in digital form

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Monitoring And Testing Of Exchanges (AREA)

Abstract

PURPOSE:To test both circuits, finding a real number part, and finding an imaginary number part, in a discrete Fourier transformation circuit, by finding the absolute value of a discrete Fourier transformation output and comparing the value with a threshold value. CONSTITUTION:An input singal from an input terminal 1 is inputted to a circuit 2 which finds the real number part of discrete Fourier transformation DFT, and a circuit 3 which finds the imaginary number part of the DFT. While the circuits 2 and 3 are in normal operation, the output of a circuit 6 which finds the absolute value of a discrete Fourier transformation output is fixed with out reference to its phase. If however, the circuit 2 has a fault to cease its output 4, the output of the circuit 6 becomes equal to that of the circuit 3, and when the circuit 3 has a fault, the output of the circuit 6 becomes equal to the output 4 of the circuit 2. For the purpose, a relation between the threshold value 8 and phase of a comparing circuit 9 is selected adequately; when both the circuits operate normally, the output 7 of the circuit 6 increases above the threshold value 8 and when either one of the circuits 2 and 3 has a fault, the output 7 of the circuit 6 becomes less than the threshold value 8, so that the fault is detected.
JP56029714A 1981-03-02 1981-03-02 Self-testing system for multifrequency signal receiver Granted JPS57143970A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56029714A JPS57143970A (en) 1981-03-02 1981-03-02 Self-testing system for multifrequency signal receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56029714A JPS57143970A (en) 1981-03-02 1981-03-02 Self-testing system for multifrequency signal receiver

Publications (2)

Publication Number Publication Date
JPS57143970A true JPS57143970A (en) 1982-09-06
JPH0343819B2 JPH0343819B2 (en) 1991-07-03

Family

ID=12283770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56029714A Granted JPS57143970A (en) 1981-03-02 1981-03-02 Self-testing system for multifrequency signal receiver

Country Status (1)

Country Link
JP (1) JPS57143970A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52106614A (en) * 1976-03-04 1977-09-07 Fujitsu Ltd Signal detection

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52106614A (en) * 1976-03-04 1977-09-07 Fujitsu Ltd Signal detection

Also Published As

Publication number Publication date
JPH0343819B2 (en) 1991-07-03

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