JPH0343819B2 - - Google Patents

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Publication number
JPH0343819B2
JPH0343819B2 JP56029714A JP2971481A JPH0343819B2 JP H0343819 B2 JPH0343819 B2 JP H0343819B2 JP 56029714 A JP56029714 A JP 56029714A JP 2971481 A JP2971481 A JP 2971481A JP H0343819 B2 JPH0343819 B2 JP H0343819B2
Authority
JP
Japan
Prior art keywords
circuit
input
fourier transform
sine wave
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56029714A
Other languages
Japanese (ja)
Other versions
JPS57143970A (en
Inventor
Akira Fukui
Shiro Kikuchi
Masaki Ehata
Makoto Mori
Takaaki Oosaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP56029714A priority Critical patent/JPS57143970A/en
Publication of JPS57143970A publication Critical patent/JPS57143970A/en
Publication of JPH0343819B2 publication Critical patent/JPH0343819B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q1/00Details of selecting apparatus or arrangements
    • H04Q1/18Electrical details
    • H04Q1/30Signalling arrangements; Manipulation of signalling currents
    • H04Q1/44Signalling arrangements; Manipulation of signalling currents using alternate current
    • H04Q1/444Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies
    • H04Q1/45Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling
    • H04Q1/457Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling with conversion of multifrequency signals into digital signals
    • H04Q1/4575Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling with conversion of multifrequency signals into digital signals which are transmitted in digital form

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Monitoring And Testing Of Exchanges (AREA)

Description

【発明の詳細な説明】 本発明は離散的フーリエ変換(以下DFTとい
う)により信号の有無を検出する多周波信号受信
器の自律試験方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an autonomous testing method for a multi-frequency signal receiver that detects the presence or absence of a signal using a discrete Fourier transform (hereinafter referred to as DFT).

従来、DFT回路の試験は、正弦波を入力して
DFTの出力を任意の閾値と比較することにより
行なつているが、DFTの核の位相と、入力する
正弦波の位相が非同期であつたり、同期していて
も両者の位相がπ/2ラジアンの整数倍であつた
りすると、DFT回路実部を求める回路と虚部を
求める回路のいずれかに障害があつても、その障
害を検出できないことがあつた。
Traditionally, DFT circuits are tested by inputting a sine wave.
This is done by comparing the output of the DFT with an arbitrary threshold, but it is possible that the phase of the DFT nucleus and the phase of the input sine wave are asynchronous, or even if they are synchronized, the phase of both is π/2 radian. If it was an integer multiple of , even if there was a fault in either the circuit for calculating the real part of the DFT circuit or the circuit for calculating the imaginary part, the failure could not be detected.

本発明の目的は、かかる問題を解決し、DFT
回路の実部を求める回路と虚部を求める回路の両
方を同時に試験可能とした多周波信号受信器の自
律試験方式を提供することにある。
The purpose of the present invention is to solve such problems and to
An object of the present invention is to provide an autonomous testing method for a multi-frequency signal receiver, which allows simultaneous testing of both a circuit for determining the real part of the circuit and a circuit for determining the imaginary part of the circuit.

本発明の多周波信号受信器の自律試験方式は、
DFTにより、信号の有無を検出する多周波信号
受信器において、DFTの核の正弦波および余弦
波に対し、π/2ラジアンの整数倍でない値だけ
位相の異なる正弦波をDFT回路に入力し、該入
力正弦波のDFTの絶対値より小さく該入力正弦
波のDFTの実部および虚部より大きい値を閾値
とし、前記正弦波を入力した時のDFT回路の出
力と前記閾値を比較することを特徴とする。
The autonomous test method of the multi-frequency signal receiver of the present invention is as follows:
In a multi-frequency signal receiver that detects the presence or absence of a signal by DFT, a sine wave whose phase differs from the DFT core sine wave and cosine wave by a value that is not an integral multiple of π/2 radians is input to the DFT circuit, A value smaller than the absolute value of the DFT of the input sine wave and larger than the real and imaginary parts of the DFT of the input sine wave is set as a threshold, and the output of the DFT circuit when the sine wave is input is compared with the threshold. Features.

また、本発明の多周波信号受信器の自律試験方
式は、DFTの自乗により、信号の有無を検出す
る多周波信号受信器において、DFTの核の正弦
波および余弦波に対し、π/2ラジアンの整数倍
でない値だけ位相の異なる正弦波をDFTの自乗
を得る回路に入力し、該入力正弦波のDFTの自
乗より小さく、該入力正弦波の実部の自乗および
虚部の自乗より大きい値を閾値とし、前記正弦波
を入力した時のDFTの自乗を得る回路の出力と
前記閾値を比較することを特徴とする。
In addition, the autonomous test method for a multifrequency signal receiver of the present invention is such that in a multifrequency signal receiver that detects the presence or absence of a signal by the square of the DFT, π/2 radian is applied to the core sine wave and cosine wave of the DFT. A sine wave whose phase differs by a value that is not an integer multiple of is input to a circuit that obtains the square of the DFT, and the value is smaller than the square of the DFT of the input sine wave and larger than the square of the real part and the square of the imaginary part of the input sine wave. is a threshold value, and the output of a circuit that obtains the square of the DFT when the sine wave is input is compared with the threshold value.

いづれの方式においても、DFT出力(又は
DFTの2乗)が閾値より小さい場合に受信器が
障害であることが分る。
In either method, DFT output (or
DFT squared) is smaller than the threshold, it is known that the receiver is at fault.

次に図面を参照して本発明を説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明が適用される多周波信号受信器
の一実施例を示すブロツク図である。この受信器
はDFTによるもので、入力端子1からの入力信
号はDFTの実部を求める回路2およびDFTの虚
部を求める回路3に入力される。DFTの実部を
求める回路2からのDFTの実部出力4とDFTの
虚部出力5とは絶対値を求める回路6に入力さ
れ、DFTの絶対値出力7が出力される。絶対値
出力7と閾値8とは比較回路9で比較され、出力
端子10には比較結果が出力される。
FIG. 1 is a block diagram showing an embodiment of a multi-frequency signal receiver to which the present invention is applied. This receiver is based on DFT, and an input signal from an input terminal 1 is input to a circuit 2 for calculating the real part of DFT and a circuit 3 for calculating the imaginary part of DFT. The DFT real part output 4 and the DFT imaginary part output 5 from the DFT real part determining circuit 2 are input to the absolute value determining circuit 6, and the DFT absolute value output 7 is output. The absolute value output 7 and the threshold value 8 are compared in a comparator circuit 9, and the comparison result is outputted to an output terminal 10.

回路2および3は各々、乗算器、加算器、シフ
トレジスタ(又はメモリ)で構成され、回路2に
はおDFTの核の正弦波が与えられ、回路3には
DFTの核の余弦波が与えられている。また、回
路6は実部出力4、虚部出力5を各々自乗するた
めの2つの乗算器と、これらの自乗結果を加算す
る加算器と、入力データをアドレスとして予め記
憶している平方根の値を出力するROMとを備え
ている。
Circuits 2 and 3 each consist of a multiplier, an adder, and a shift register (or memory), and circuit 2 is given the core sine wave of the DFT, and circuit 3 is
The core cosine wave of the DFT is given. Further, the circuit 6 includes two multipliers for squaring the real part output 4 and the imaginary part output 5, an adder for adding these squared results, and a square root value whose input data is stored in advance as an address. It is equipped with a ROM that outputs.

この第1図において、回路構成そのものは公知
であるが、入力端子1から入力される波形によつ
ては、たとえ回路2,3が障害であつてもこれを
検出することが不可能なことがある。
In FIG. 1, the circuit configuration itself is well known, but depending on the waveform input from input terminal 1, even if there is a fault in circuits 2 and 3, it may be impossible to detect it. be.

したがつて、本願方式では信号受信器の自律試
験時にこの受信器に入力する波形の条件を特定す
ることにより、受信器の障害を正しく検出できる
ようにしている。
Therefore, in the system of the present application, failures in the receiver can be detected correctly by specifying the conditions of the waveform input to the signal receiver during an autonomous test of the signal receiver.

次に第1図と第2図とを併せ参照して本発明の
試験方式を説明する。
Next, the test method of the present invention will be explained with reference to FIGS. 1 and 2.

第2図は、第1図の入力端子1に、DFTの核
の正弦波と位相がθだけ異なる正弦波を入力した
時の、DFTの実部4、虚部5、絶対値7の値を
縦軸に、位相θを横軸にして示した図である。
Figure 2 shows the values of the real part 4, imaginary part 5, and absolute value 7 of the DFT when a sine wave whose phase differs by θ from the core sine wave of the DFT is input to input terminal 1 in Figure 1. It is a diagram in which the vertical axis represents the phase θ and the horizontal axis represents the phase θ.

まず、DFTの実部を求める回路2および虚部
を求める回路3が正常に動作している場合は、絶
対値を求める回路6の出力が第2図の7となり、
位相θによらず一定である。ところが、DFTの
実部を求める回路2に障害があつて、その出力4
が零になると、絶対値を求める回路6の出力は、
DFTの虚部出力5と同じになり、又DFTの虚部
を求める回路3に障害があつて、その出力が零に
なると絶対値を求める回路6の出力は実部4と同
じになる。従つて、閾値8と位相θの関係を第2
図の斜線で示した領域11の範囲内に選べば、正
常時には絶対値を求める回路6の出力7は、閾値
8以上となり、DFTの実部を求める回路2と虚
部を求める回路3のいずれかが障害の時には閾値
8以下となることにより障害を検出できる。
First, if the circuit 2 for calculating the real part of DFT and the circuit 3 for calculating the imaginary part are operating normally, the output of the circuit 6 for calculating the absolute value will be 7 in Fig. 2,
It is constant regardless of the phase θ. However, there is a failure in circuit 2 that calculates the real part of DFT, and its output 4
When becomes zero, the output of the circuit 6 that calculates the absolute value is
It becomes the same as the imaginary part output 5 of the DFT, and if there is a failure in the circuit 3 for calculating the imaginary part of the DFT and its output becomes zero, the output of the circuit 6 for calculating the absolute value will be the same as the real part 4. Therefore, the relationship between the threshold value 8 and the phase θ is expressed as
If it is selected within the shaded area 11 in the figure, the output 7 of the circuit 6 for calculating the absolute value will be equal to or higher than the threshold value 8 under normal conditions, and the circuit 2 for calculating the real part of DFT and the circuit 3 for calculating the imaginary part will be selected. In the event of a failure, the failure can be detected when the threshold value is equal to or less than 8.

このように、本願方式の自律試験時に入力され
る波形すなわち、DFTの核の正弦波および余弦
波に対してπ/2ラジアンの整数倍でない値だけ
位相の異なる正弦波を作成する手段の一例につい
て説明する。
As described above, an example of a means for creating a sine wave whose phase differs from the waveform input during the autonomous test of the present method, that is, the sine wave and cosine wave of the DFT core by a value that is not an integral multiple of π/2 radians. explain.

例えば、第3図に示すような波形発生回路11
により作成される波形を受信器に入力する。回路
11は3つのN進カウンタ12〜14とこれらカ
ウンタの出力を時分割に選択して出力するセレク
タ15と、このセレクタ15の出力をアドレス入
力として記憶内容を出力する正弦波ROM16
と、このROM16の出力をラツチして出力する
3つのラツチ回路18〜20と、セレクタ15お
よびラツチ回路18〜20の動作タイミングを制
御するタイミングコントローラ17とから構成さ
れている。正弦波ROM16の内容は第4図に示
すように、正弦波周期2πに対応するアドレス0
〜N−1に振幅値−1〜1がコード化されて記憶
されている。この構成において、カウンタ12,
13,14の初期値を各々第4図のA(0ラジア
ンに対応)、B(π/4ラジアンに対応)、C(π/
2ラジアンに対応)に設定し、セレクタ15によ
つてカウンタ12の出力が選択されているときに
は正弦波ROM16の出力をラツチ回路18での
みラツチし、第1図におけるDFTの核の正弦波
Aとして信号受信器に入力するようタイミングコ
ントローラ17でセレクタ15、ラツチ回路18
〜20を制御する。タイミングコントローラ17
の制御により、セレクタ15は周期的に入力を切
替え、これに同期して3つのラツチ回路18〜2
0の1つでROM16の出力がラツチされる。す
なわち、カウンタBによりROM16から読み出
された出力はラツチ回路19でラツチされ、本発
明による自律試験時に障害を検出するための試験
入力波Bとして第1図の入力端子1に入力され
る。また、カウンタCによりROM16から読み
出された出力はラツチ回路20でラツチされ、第
1図におけるDFTの核の余弦波Cとして信号受
信器に入力される。なお、第4図の説明では試験
用入力正弦波Bは正弦波Aよりπ/4ラジアン位
相が異なつているが、この位相のずれはこの値に
限定されず、π/2の整数倍でなければ本願発明
の効果は達成できる。
For example, a waveform generation circuit 11 as shown in FIG.
The waveform created by is input to the receiver. The circuit 11 includes three N-ary counters 12 to 14, a selector 15 that selects and outputs the outputs of these counters in a time-division manner, and a sine wave ROM 16 that uses the output of the selector 15 as an address input and outputs the stored contents.
, three latch circuits 18-20 that latch and output the output of the ROM 16, and a timing controller 17 that controls the operation timing of the selector 15 and the latch circuits 18-20. The contents of the sine wave ROM 16 are as shown in FIG.
~N-1, amplitude values -1 to 1 are encoded and stored. In this configuration, the counter 12,
The initial values of 13 and 14 are respectively A (corresponding to 0 radian), B (corresponding to π/4 radian), and C (π/4 radian) in Figure 4.
2 radians), and when the output of the counter 12 is selected by the selector 15, the output of the sine wave ROM 16 is latched only by the latch circuit 18, and the sine wave A of the core of the DFT in FIG. The timing controller 17 controls the selector 15 and latch circuit 18 to input the signal to the receiver.
~20 controls. timing controller 17
Under the control of
One of the zeros latches the output of ROM16. That is, the output read from the ROM 16 by the counter B is latched by the latch circuit 19 and inputted to the input terminal 1 of FIG. 1 as the test input wave B for detecting a fault during the autonomous test according to the present invention. Further, the output read from the ROM 16 by the counter C is latched by the latch circuit 20 and inputted to the signal receiver as the core cosine wave C of the DFT in FIG. In addition, in the explanation of FIG. 4, the test input sine wave B has a phase difference of π/4 radians from the sine wave A, but this phase shift is not limited to this value, and must be an integral multiple of π/2. If so, the effects of the present invention can be achieved.

以上の実施例ではDFTの実部および虚部出力
と閾値を比較することにより信号の有無を検出す
る多周波信号受信器について説明したが、実部を
求める回路を実部の自乗を求める回路、虚部を求
める回路を虚部の自乗を求める回路、絶対値を求
める回路6を加算回路としても、同様な結果が得
られる。
In the above embodiment, a multi-frequency signal receiver that detects the presence or absence of a signal by comparing the real and imaginary part outputs of DFT with a threshold value has been described. Similar results can be obtained by using the circuit for calculating the imaginary part as a circuit for calculating the square of the imaginary part, and the circuit 6 for calculating the absolute value as an adding circuit.

本発明は以上説明したように、入力正弦波と
DFTの核の位相と閾値の関係を設定すれば、従
来の試験法と同程度のハード量でDFTの実部を
求める回路と虚部を求める回路のいずれかに障害
があつても、その障害を検出することができる効
果がある。
As explained above, the present invention uses an input sine wave and
By setting the relationship between the phase of the DFT nucleus and the threshold, even if there is a fault in either the circuit that calculates the real part or the circuit that calculates the imaginary part of the DFT, it can be detected with the same amount of hardware as in the conventional test method. It is effective in detecting

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロツク図、
第2図は第1図の各部の出力の関係を示す図、第
3図は第1図の受信器に入力される波形を作成す
る回路の一例を示す図、第4図は第3図の動作を
説明する図である。 1:入力端子、2:離散的フーリエ変換の実部
を求める回路、3:離散的フーリエ変換の虚部を
求める回路、4:回路2の出力、5:回路3の出
力、6:絶対値を求める回路、7:絶対値を求め
る回路の出力、8:閾値、9:比較回路、10:
出力端子。
FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 is a diagram showing the relationship between the outputs of each part in Figure 1, Figure 3 is an example of a circuit that creates the waveform input to the receiver in Figure 1, and Figure 4 is the diagram shown in Figure 3. It is a figure explaining operation. 1: Input terminal, 2: Circuit for calculating the real part of the discrete Fourier transform, 3: Circuit for calculating the imaginary part of the discrete Fourier transform, 4: Output of circuit 2, 5: Output of circuit 3, 6: Absolute value Circuit for obtaining absolute value, 7: Output of circuit for obtaining absolute value, 8: Threshold value, 9: Comparison circuit, 10:
Output terminal.

Claims (1)

【特許請求の範囲】 1 離散的フーリエ変換により、信号の有無を検
出する多周波信号受信器において、離散的フーリ
エ変換の核の正弦波および余弦波に対し、π/2
ラジアンの整数倍でない値だけ位相の異なる正弦
波を離散的フーリエ変換回路に入力し、該入力正
弦波の離散的フーリエ変換の絶対値より小さく該
入力正弦波の離散的フーリエ変換の実部および虚
部より大きい値を閾値とし、前記正弦波を入力し
た時の離散的フーリエ変換回路の出力と前記閾値
を比較して前記出力が前記閾値よりい小さい場合
に前記受信器の障害とすることを特徴とする多周
波信号受信器の自律試験方式。 2 離散的フーリエ変換の自乗により、信号の有
無を検出する多周波信号受信器において、離散的
フーリエ変換の核の正弦波および余弦波に対し、
π/2ラジアンの整数倍でない値だけ位相の異な
る正弦波を離散的フーリエ変換の自乗を得る回路
に入力し、該入力正弦波の離散的フーリエ変換の
自乗より小さく、該入力正弦波の離散的フーリエ
変換の実部の自乗および虚部の自乗より大きい値
を閾値とし、前記正弦波を入力したときの離散的
フーリエ変換の自乗を得る回路の出力と前記閾値
を比較して前記出力が前記閾値より小さい場合に
前記受信器の障害とすることを特徴とする多周波
信号受信器の自律試験方式。
[Claims] 1. In a multi-frequency signal receiver that detects the presence or absence of a signal by discrete Fourier transform, π/2
Sine waves whose phases differ by a value that is not an integer multiple of radians are input to a discrete Fourier transform circuit, and the real and imaginary parts of the discrete Fourier transform of the input sine wave are smaller than the absolute value of the discrete Fourier transform of the input sine wave. A value larger than the threshold is set as a threshold, and an output of the discrete Fourier transform circuit when the sine wave is input is compared with the threshold, and if the output is smaller than the threshold, the receiver is determined to be at fault. An autonomous test method for multi-frequency signal receivers. 2. In a multi-frequency signal receiver that detects the presence or absence of a signal by the square of the discrete Fourier transform, for the core sine wave and cosine wave of the discrete Fourier transform,
A sine wave whose phase differs by a value that is not an integer multiple of π/2 radians is input to a circuit that obtains the square of the discrete Fourier transform, and is smaller than the square of the discrete Fourier transform of the input sine wave, and whose phase differs by a value that is not an integer multiple of π/2 radians. A value larger than the square of the real part and the square of the imaginary part of the Fourier transform is set as a threshold, and the output of a circuit that obtains the square of the discrete Fourier transform when the sine wave is input is compared with the threshold, and the output is determined to be the threshold. An autonomous test method for a multi-frequency signal receiver, characterized in that a failure of the receiver is determined when the signal is smaller than that of the receiver.
JP56029714A 1981-03-02 1981-03-02 Self-testing system for multifrequency signal receiver Granted JPS57143970A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56029714A JPS57143970A (en) 1981-03-02 1981-03-02 Self-testing system for multifrequency signal receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56029714A JPS57143970A (en) 1981-03-02 1981-03-02 Self-testing system for multifrequency signal receiver

Publications (2)

Publication Number Publication Date
JPS57143970A JPS57143970A (en) 1982-09-06
JPH0343819B2 true JPH0343819B2 (en) 1991-07-03

Family

ID=12283770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56029714A Granted JPS57143970A (en) 1981-03-02 1981-03-02 Self-testing system for multifrequency signal receiver

Country Status (1)

Country Link
JP (1) JPS57143970A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52106614A (en) * 1976-03-04 1977-09-07 Fujitsu Ltd Signal detection

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52106614A (en) * 1976-03-04 1977-09-07 Fujitsu Ltd Signal detection

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JPS57143970A (en) 1982-09-06

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