JPS57140009A - Bias circuit for field effect transistor - Google Patents

Bias circuit for field effect transistor

Info

Publication number
JPS57140009A
JPS57140009A JP56025736A JP2573681A JPS57140009A JP S57140009 A JPS57140009 A JP S57140009A JP 56025736 A JP56025736 A JP 56025736A JP 2573681 A JP2573681 A JP 2573681A JP S57140009 A JPS57140009 A JP S57140009A
Authority
JP
Japan
Prior art keywords
power
gate
resistor
power supply
fet1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56025736A
Other languages
Japanese (ja)
Inventor
Shigenobu Aihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56025736A priority Critical patent/JPS57140009A/en
Publication of JPS57140009A publication Critical patent/JPS57140009A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To achieve stable operation against parameter fluctuation of an FET and high efficiency, by connecting a low voltage power supply at a split point of a split resistor inserted between the source and gate of the FET and a high impedance high voltage power supply to the gate.
CONSTITUTION: Split resistors 2' and 3 are inserted between the source and gate of an FET1, a split point is connected to a low voltage 4' and a high impedance power supply 5 is connected to the gate of the FET1. In this automatic bias circuit, when biasing is made, the power required for biasing the FET1 requires the required minimum power plus a power consumed in the resistor 2' to obtain a voltage VGS between the gate and source. The power efficiency can be increased by supplying a potential required for this VGS from the other high impedance power supply 5 without consumed power more than required power in the resistor 2'. Since the increase in the current IS flowing to the resistor 2' is fed back to the VGS through the resistor 2' through the connection, stable operation can be made against parameter fluctuation.
COPYRIGHT: (C)1982,JPO&Japio
JP56025736A 1981-02-24 1981-02-24 Bias circuit for field effect transistor Pending JPS57140009A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56025736A JPS57140009A (en) 1981-02-24 1981-02-24 Bias circuit for field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56025736A JPS57140009A (en) 1981-02-24 1981-02-24 Bias circuit for field effect transistor

Publications (1)

Publication Number Publication Date
JPS57140009A true JPS57140009A (en) 1982-08-30

Family

ID=12174096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56025736A Pending JPS57140009A (en) 1981-02-24 1981-02-24 Bias circuit for field effect transistor

Country Status (1)

Country Link
JP (1) JPS57140009A (en)

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