JPS57138170A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS57138170A
JPS57138170A JP56023015A JP2301581A JPS57138170A JP S57138170 A JPS57138170 A JP S57138170A JP 56023015 A JP56023015 A JP 56023015A JP 2301581 A JP2301581 A JP 2301581A JP S57138170 A JPS57138170 A JP S57138170A
Authority
JP
Japan
Prior art keywords
circuit
circuits
thin
constitution
linear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56023015A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0377666B2 (enrdf_load_stackoverflow
Inventor
Mikio Haijima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56023015A priority Critical patent/JPS57138170A/ja
Publication of JPS57138170A publication Critical patent/JPS57138170A/ja
Publication of JPH0377666B2 publication Critical patent/JPH0377666B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65Integrated injection logic
    • H10D84/658Integrated injection logic integrated in combination with analog structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Logic Circuits (AREA)
JP56023015A 1981-02-20 1981-02-20 Semiconductor integrated circuit device Granted JPS57138170A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56023015A JPS57138170A (en) 1981-02-20 1981-02-20 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56023015A JPS57138170A (en) 1981-02-20 1981-02-20 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS57138170A true JPS57138170A (en) 1982-08-26
JPH0377666B2 JPH0377666B2 (enrdf_load_stackoverflow) 1991-12-11

Family

ID=12098659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56023015A Granted JPS57138170A (en) 1981-02-20 1981-02-20 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS57138170A (enrdf_load_stackoverflow)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6113319A (ja) * 1984-06-29 1986-01-21 Yokogawa Hokushin Electric Corp 基準電圧発生装置
JPS61190150U (enrdf_load_stackoverflow) * 1985-05-17 1986-11-27
JPS63142847A (ja) * 1986-12-05 1988-06-15 Nec Corp 半導体集積回路
JPH0685030A (ja) * 1992-09-07 1994-03-25 Hitachi Ltd 半導体集積回路
US7208923B2 (en) 2003-09-08 2007-04-24 Rohm Co., Ltd. Multiple-output power device, and mobile device using the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5499576U (enrdf_load_stackoverflow) * 1977-12-26 1979-07-13
JPS54142985A (en) * 1978-04-28 1979-11-07 Toshiba Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5499576U (enrdf_load_stackoverflow) * 1977-12-26 1979-07-13
JPS54142985A (en) * 1978-04-28 1979-11-07 Toshiba Corp Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6113319A (ja) * 1984-06-29 1986-01-21 Yokogawa Hokushin Electric Corp 基準電圧発生装置
JPS61190150U (enrdf_load_stackoverflow) * 1985-05-17 1986-11-27
JPS63142847A (ja) * 1986-12-05 1988-06-15 Nec Corp 半導体集積回路
JPH0685030A (ja) * 1992-09-07 1994-03-25 Hitachi Ltd 半導体集積回路
US7208923B2 (en) 2003-09-08 2007-04-24 Rohm Co., Ltd. Multiple-output power device, and mobile device using the same

Also Published As

Publication number Publication date
JPH0377666B2 (enrdf_load_stackoverflow) 1991-12-11

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